2096E_1 Datasheet, PDF (5/11 Pages) Lattice Semiconductor – In-System Programmable SuperFAST™ High Density PLD

Specifications ispLSI 2096E
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER
TEST
COND.⁴
#²
DESCRIPTION¹
-180
-135
-100
UNITS
MIN. MAX. MIN. MAX. MIN. MAX.
tpd1
A 1 Data Prop Delay, 4PT Bypass, ORP Bypass
– 5.0 – 7.5 – 10.0 ns
tpd2
A 2 Data Prop Delay
– 7.5 – 10.0 – 13.0 ns
fmax
A 3 Clk Freq with Internal Feedback³
180 – 135 – 100 – MHz
fmax (Ext.)
fmax (Tog.)
–
4
Clk
Freq
with
External
Feedback
(1
tsu2 +
) _tco1
– 5 Clk Frequency, Max. Toggle
125 – 100 – 77 –
200 – 143 – 100 –
MHz
MHz
tsu1
–
6 GLB Reg Setup Time before Clk, 4 PT Bypass 4.0 – 5.0 – 6.5 –
ns
tco1
A 7 GLB Reg Clk to Output Delay, ORP Bypass
– 3.0 – 4.0 – 5.0 ns
th1
– 8 GLB Reg Hold Time after Clk, 4 PT Bypass
0.0 – 0.0 – 0.0 –
ns
tsu2
– 9 GLB Reg Setup Time before Clk
5.0 – 6.0 – 8.0 –
ns
tco2
– 10 GLB Reg Clk to Output Delay
– 3.5 – 4.5 – 6.0 ns
th2
– 11 GLB Reg Hold Time after Clk
0.0 – 0.0 – 0.0 –
ns
tr1
A 12 External Reset Pin to Output Delay
– 7.0 – 10.0 – 13.5 ns
trw1
– 13 External Reset Pulse Duration
4.0 – 5.0 – 6.5 –
ns
tptoeen
B 14 Input to Output Enable
– 10.0 – 12.0 – 15.0 ns
tptoedis
C 15 Input to Output Disable
– 10.0 – 12.0 – 15.0 ns
tgoeen
B 16 Global OE Output Enable
– 5.0 – 7.0 – 9.0 ns
tgoedis
C 17 Global OE Output Disable
– 5.0 – 7.0 – 9.0 ns
twh
– 18 External Synch Clk Pulse Duration, High
2.5 – 3.5 – 5.0 –
ns
twl
– 19 External Synch Clk Pulse Duration, Low
2.5 – 3.5 – 5.0 –
ns
1. Unless noted otherwise, all parameters use a GRP load of four GLBs, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
Table 2-0030A/2096E
5