2096E_1 Datasheet, PDF (7/11 Pages) Lattice Semiconductor – In-System Programmable SuperFAST™ High Density PLD

Specifications ispLSI 2096E
ispLSI 2096E Timing Model
I/O Cell
GRP
Ded. In
I/O Pin
(Input)
#21
I/O Delay
#20
GRP
#22
#45
Reset
GLB
Feedback
Comb 4 PT Bypass #23
Reg 4 PT Bypass
#24
GLB Reg Bypass
#28
20 PT
XOR Delays
#25 - 27
GLB Reg
Delay
D
Q
RST
#29 - 32
ORP
I/O Cell
ORP Bypass
#37
#38,
#39
I/O Pin
(Output)
ORP
Delay
#36
Y0,1,2
GOE0, 1
#43, 44
#42
Control _RE
PTs
OE
#33 - 35 CK
Derivations of tsu, th and tco from the Product Term Clock
tsu
= Logic + Reg su - Clock (min)
= (tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min))
= (#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
3.6 = (0.5 + 0.6 + 3.9) + (0.7) - (0.5 + 0.6 + 1.0)
th
= Clock (max) + Reg h - Logic
= (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor)
= (#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
3.4 = (0.5 + 0.6 + 4.0) + (3.3) - (0.5 + 0.6 + 3.9)
tco
= Clock (max) + Reg co + Output
= (tio + tgrp + tptck(max)) + (tgco) + (torp + tob)
= (#20 + #22 + #35) + (#31) + (#36 + #38)
7.9 = (0.5 + 0.6 + 4.0) + (0.3) + (0.9 + 1.6)
Table 2-0042/2096E
Note: Calculations are based upon timing specifications for the ispLSI 2096E-180L.
#40, 41
0491/2096E
7