PAC80 Datasheet, PDF (7/19 Pages) Lattice Semiconductor – In-System Programmable Analog Circuit

Specifications ispPAC80
Pin Descriptions
Pin(s) Symbol
1
TMS
2
TCK
3
TDI
Name
Test Mode Select
Test Clock
Test Data In
4
TDO
Test Data Out
5
CS
6
CAL
7 ENSPI
8
GND
9 VREFout
10, 11 IN
Chip Select
Auto-Calibrate
Enable SPI Mode
Ground
Common-Mode
Reference
Inputs (+ or -)
12, 15 TEST
13, 14 OUT
Test Pin
Outputs (+ or -)
16
VS
Supply Voltage
Description
Serial interface logic mode select pin (input). JTAG interface mode only.
Serial interface logic clock pin (input). JTAG interface mode only.
Serial interface logic pin (input) for both JTAG and SPI operation modes.
Input data valid on rising edge of TCK (JTAG), or on rising edge of CS (SPI).
Serial interface logic pin (output) for both JTAG and SPI operation modes.
Input data valid on falling edge of TCK (JTAG), or on rising edge of CS (SPI).
Chip select logic input pin. SPI data latch.
Digital pin (input). Commands an auto-calibration sequence on a rising edge.
Enable SPI logic input pin. When high, causes serial port to run in SPI mode.
Ground pin. Should normally be connected to the analog ground plane.
Common-mode voltage reference output pin (+2.5V nominal). Must be
bypassed to GND with a 1µF capacitor.
Differential input pins, using two pins (e.g., IN+ and IN-). Plus or minus
components of V_IN, where differential V_IN = V_IN+ - V_IN-.
Test pin. Connect to GND for proper circuit operation.
Differential output pins, using two pins (e.g., OUT+ and OUT-).
Complementary with respect to V_REFOUT. Differential V_OUT = V_OUT+ - V_OUT-.
Analog supply voltage pin (5V nominal). Should be bypassed to GND with 1µF
and .01µF capacitors.
Connection Notes
1. All inputs and outputs are labeled with plus (+) and minus (-) signs. Polarity is labeled for reference and can be
selected externally by reversing pin connections.
2. All analog output pins are “hard-wired” to internal output devices and should be left open if not used. V_OUT+ and
V_OUT- should not be tied together as unnecessary power will be dissipated.
3. When the signal input is single-ended, the other half of the unused differential input must be connected to a DC
common-mode reference (usually V_REFOUT, 2.5V).
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