PAC80 Datasheet, PDF (12/19 Pages) Lattice Semiconductor – In-System Programmable Analog Circuit

Specifications ispPAC80
Software-Based Design Environment
Design Entry Software
Designers configure the ispPAC80 and verify its perfor-
mance using PAC-Designer, an easy-to-use, Microsoft
Windows compatible program. Circuit designs are en-
tered graphically and then verified, all within the
PAC-Designer environment. Full device programming is
supported using PC parallel port I/O operations and a
download cable connected to the serial programming
interface of the ispPAC80. A database of filter configura-
tions is included with thousands of possible
implementations to choose from. In addition, compre-
hensive on-line and printed documentation is provided
that covers all aspects of PAC-Designer operation.
and output pins are represented. Static or non-
configurable pins such as power, ground, V_REFOUT, and
the serial digital interface are omitted for clarity. Any
element in the schematic window can be accessed via
mouse operations as well as menu commands. When
completed, configurations can be saved, simulated, and
downloaded to devices.
PAC-Designer operation can be automated and ex-
tended by using custom-designed Visual Basic™
programs that set the interconnections and the param-
eters of ispPAC products. More information on this and
other topics is included in the on-line documentation as
well as the PAC-Designer Getting Started Manual.
The PAC-Designer schematic window, shown in Figure
2, provides access to all configurable ispPAC80 ele-
ments via its graphical user interface. All analog input
Figure 2. Initial PAC-Designer Schematic Design Entry Screen
Design1
5th Order
IN
IA
Lowpass Filter
OA
PACell
1, 2, 5, 10
A/B 2:1 Mux
OUT
Type=Butterworth
Fc=500.0kHz
Fp=
Cfg A
PB Ripple=
SB Atten.=
Type=Elliptic
Fc=50.0kHz
Fp=75.0kHz
Cfg B
PB Ripple=0.1dB
SB Atten.=-40.0dB
C1
Cfg A 1.970
C2
0.000
L2
5.140
C3
6.332
C4
0.000
L4
5.256
C5
1.020
Cfg B 32.113 4.890 38.492 66.918 14.726 28.512 17.486
12