PAC80 Datasheet, PDF (18/19 Pages) Lattice Semiconductor – In-System Programmable Analog Circuit

Specifications ispPAC80
IEEE Standard 1149.1 Interface (Continued)
retention is given in the TAP signal specifications table.
The user must ensure that the recommended program-
ming times are observed. The bit code for these
instructions is shown in Table 5.
VERA and VERB (verify user A or B) are the next Lattice
instructions and cause the current A or B configurations
of the ispPAC80 to be loaded into the user register. This
operation doesn’t interrupt operation of the device. The
current configuration of either the A or B configuration
memory can then be shifted out of the user register
immediately after an ADDUSR instruction is executed.
NOTE: The verification of memory configuration “A” is
possible only when the A/B bit is set to a logic 0. This must
be taken into account if verify will be performed at a later
time on parts with unknown configurations (refer to the
Lattice application note covering the required algorithms
necessary for complete JTAG device programming con-
trol of the ispPAC80, specific bit assignments, word
lengths, etc.). If the A/B bit has been set to a logic 1, it will
not be possible to do a VERA command properly. The bit
code for this instruction is shown in Table 5.
ENCAL (enable calibration) is a Lattice instruction that
enables the start of an auto-calibration sequence. This
operation causes all outputs of the device to go to 2.5V
until the calibration sequence is completed (see timing
specifications). As with the programming instructions
above, calibration does not begin until entry of the Run-
Test/Idle state. The completion of the calibration is not
dependent, however, on any further TAP control. This
means the state of the TAP can be returned immediately
to the Test-Logic-Reset state. The only consideration
would be to not clock the TAP during critical analog
operations. The first several milliseconds of the calibra-
tion routine are consumed waiting for configurations to
settle, though, leaving more than enough time to clock
the TAP back to the Test-Logic-Reset state. The bit code
for this instruction is shown in Table 5.
The last Lattice instructions are ABE and BBE (user A or
B bulk erase). Operation of the device is interrupted
during an ABE or BBE, during which all inputs are
disconnected and all outputs driven to VREFOUT (2.5V).
To economize internal circuitry, programming can only
be selectively done in one direction (from zeroes to
ones). The ABE and BBE are used to return all user bits
to a zero state at the same time. An ABE or BBE usually
proceeds a PRGA or PRGB operation, otherwise one to
zero changes would not be implemented. It can also be
used to erase all configuration information from a device
and is the default condition of parts shipped from the
factory. The same programming time constraints apply to
ABE and BBE as for PRGA and PRGB. The bit code for
this instruction is shown in Table 5.
The ADDUSR, BYPASS, EXTEST, IDCODE and
SAMPLE/PRELOAD instructions are all executed in the
Update-IR state. Other instructions: PRGUSR, VERUSR
and UBE are executed upon entry of the Run-Test/Idle
state.
It is recommended that when all serial interface opera-
tions are completed, the TAP controller be reset and left
in the Test-Logic-Reset state (the power-up default) and
the TCK and TMS inputs idled. This will insure the best
analog performance possible by minimizing the effects of
digital logic “feed-through.”
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