PAC80 Datasheet, PDF (16/19 Pages) Lattice Semiconductor – In-System Programmable Analog Circuit

Specifications ispPAC80
IEEE Standard 1149.1 Interface (Continued)
is entered, the first action is a capture operation. For the
Data Registers, the Capture-DR state is very simple: it
captures (parallel loads) data onto the selected serial
data path (previously chosen with the appropriate in-
struction). For the Instruction Register, the Capture-IR
state will always load the IDCODE instruction. It will
always enable the ID Register for readout if no other
instruction is loaded prior to a Shift-DR operation. This,
in conjunction with mandated bit codes, allows a “blind”
interrogation of any device in a compliant IEEE 1149.1
serial chain.
From the Capture state, the TAP transitions to either the
Shift or Exit1 state. Normally the Shift state follows the
Capture state so that test data or status information can
be shifted out or new data shifted in. Following the Shift
state, the TAP either returns to the Run-Test/Idle state
via the Exit1 and Update states or enters the Pause state
via Exit1. The Pause state is used to temporarily suspend
the shifting of data through either the Data or Instruction
Register while an external operation is performed. From
the Pause state, shifting can resume by reentering the
Shift state via the Exit2 state or be terminated by entering
the Run-Test/Idle state via the Exit2 and Update states.
If the proper instruction is shifted in during a Shift-IR
operation, the next entry into Run-Test/Idle initiates the
test mode (steady state = test). This is when the device
is actually programmed, erased or verified. All other
instructions are executed in the Update state.
Test Instructions
Like data registers, the IEEE 1149.1 standard also man-
dates the inclusion of certain instructions. It outlines the
function of three required and six optional instructions.
Any additional instructions are left exclusively for the
manufacturer to determine. The instruction word length is
not mandated other than to be a minimum of 2-bits, with
only the BYPASS and EXTEST instruction code patterns
being specifically called out (all ones and all zeroes
respectively). The ispPAC80 contains the required mini-
mum instruction set as well as one from the optional
instruction set. In addition, there are several proprietary
instructions that allow the device to be configured and
verified. For ispPAC80, the instruction word length is 5-
bits. All ispPAC80 instructions available to users are
shown in Table 5.
BYPASS is one of the three required instructions. It
selects the Bypass Register to be connected between
TDI and TDO and allows serial data to be transferred
through the device without affecting the operation of the
Figure 6. Test Access Port (TAP) Contoller State Diagram
1 Test-Logic-Rst
0
1
0 Run-Test/Idle
1
Select-DR-Scan
0
1 _Capture-DR
0
Shift-DR
0
1
1
Exit1-DR
0
Pause-DR 0
1
0
Exit2-DR
1
Update-DR
1
0
1
Select-IR-Scan
0
1 _Capture-IR
0
Shift-IR
0
1
1
Exit1-IR
0
Pause-IR
0
1
0
Exit2-IR
1
Update-IR
1
0
Note: The value shown adjacent to each state transition in this figure
represents the signal present at TMS at the time of a rising edge at TCK.
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