ORSO42G5 Datasheet, PDF (63/153 Pages) Lattice Semiconductor – 0.6 to 2.7 Gbps SONET Backplane Interface FPSCs

Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
• Note that RXDxx[39:32] signal assignments are the same no matter what mode the RX blocks are in.
Table 13 summarizes the signals across the Core/FPGA interface in the receive direction.
Table 13. RX Core/FPGA Interface Signals – ORSO42G5
RXDAC[39:0]
39
38
37
SONET mode
SYNC2_A2_OOS
—
—
IPC2 A2 Mode
—
IPC2_A2_CELLDROP
IPC2_A2_CELLSTART
36
35
34
33
32
[31:20]
[19:0]
DOUTAC_FP
DOUTAC_SPE
—
DOUTAC[31:20]]
DOUTAC[19:0]
—
DOUTAC_OOF
—
IPC2_A2_CELL_BIP_ERR
DOUTAC_B1_ERR
—
IPC2_A2[39:20]
RXDAD[39:0]
39
38
37
36
35
34
33
32
[31:20]
[19:0]
SONET Mode
—
—
—
DOUTAD_FP
DOUTAD_SPE
—
DOUTAD[31:20]
DOUTAD[19:0]
IPC2 A2 Mode
—
—
CELL_BEGIN_OK_A2
—
DOUTAD_OOF
—
—
DOUTAD_B1_ERR
—
IPC2_A2[19:0]
RXDBC[39:0]
39
38
37
36
35
34
33
32
[31:20]
[19:0]
RXDBD[39:0]
39
38
37
36
35
34
SONET Mode
SYNC2_B2_OOS
—
—
DOUTBC_FP
DOUTBC_SPE
—
DOUTBC[31:20]
DOUTBC[19:0]
SONET Mode
SYNC4_B_OOS
—
DOUTBD_FP
DOUTBD_SPE
IPC2 B2 Mode
—
IPC2_B2_CELLDROP
IPC2_B2_CELLSTART
—
DOUTBC_OOF
—
IPC2_B2_CELL_BIP_ERR
DOUTBC_B1_ERR
—
IPC2_B2[39:20]
IPC2 B2 Mode
—
—
CELL_BEGIN_OK_B2
—
DOUTBD_OOF
—
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