ORSO42G5 Datasheet, PDF (60/153 Pages) Lattice Semiconductor – 0.6 to 2.7 Gbps SONET Backplane Interface FPSCs

Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
Figure 46. ORSO82G5 Receive FPGA/Embedded Core Interface IPC8 Mode
1 cycle
SYSCLK156x[1,2]
“n” clk cycles
IDLE
4 clk cycles
IPC8_CELLSTART
IPC8_[159:0]
D D D D D D D D D D D D D D D D D D D D D D D DD
IPC8_CELL_BIP_ERR
IPC8_CELLDROP
Cell Drop is associated with
the NEXT cell (NOT present)
BIP Error is associated
with CURRENT cell
CELL BIP ERROR
If a Cell BIP Error occurs, the CELL_BIP_ERR signal
reflects the occurrence, as shown in the figure.
CELL BIP ERROR
If a cell error occurs within the ASB and;
1. CELL_BIP_INH=0 (Do not drop BIP errored cells)
2. A BIP error occurs
The drop indicator will PRECEED the user cell that con-
tains the BIP error. All data will be passed w/o modifica-
tion.
In the SERDES-only mode the data are simply transferred as 32-bit wide words to and from the FPGA logic. The
next sections describe the signal definitions for the TX and RX paths in the SONET, OPC2 and OPC8 modes. The
signal names unique to an operating mode are preferred for design and are generally the ones used in the
ispLEVER design environment. The labels in the left most column are the hardware FPGA interface names. The
ispLEVER software creates an HDL module with specific names based on the mode selected for each channel.
The pin mappings performed by ispLEVER are shown in Table 11 through Table 14.
The interface signals for the embedded RAM are completely independent of these signals. The memory signals are
described in a later section.
Signal Description for TX Path (FPGA to SERDES Core) – ORSO42G5
• Signals are divided across four channels with 40 signals per channel. TXDxx[39:0] is the set of 40 signals for a
channel xx.
• The data signals multiplexing scheme is similar to the one used for the RXD signals. However, the status signals
multiplexing is different. Please refer to Table 11 for a detailed description of the TXD multiplexing scheme.
• For all channels the TXDxx[39:33] signals are not used.
Table 11 summarizes the signals at the FPGA/Core interface in the transmit direction.
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