ORSO42G5 Datasheet, PDF (11/153 Pages) Lattice Semiconductor – 0.6 to 2.7 Gbps SONET Backplane Interface FPSCs

Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
Figure 1. ORSO42G5 and ORSO82G5 Basic Chip Configuration
ORCA 4E04-Based
Programmable Logic
Embedded
Core
(4 or 8 Serial
Channels)
The ORSO42G5 and ORSO82G5 support aggregate bandwidths over 10Gbps and are targeted towards users
needing high-speed backplane interfaces for SONET and other non-SONET proprietary backplanes. For non-
SONET applications, all SONET functionality is hidden from the user and no prior networking knowledge is
required.
Built using Series 4 reconfigurable System-on-a-Chip (SoC) architecture, the ORSO42G5 and ORSO82G5 contain
the FPGA base array and an embedded core supporting eight serial data channels, with clock and data recovery
functions, and provides SONET framing, scrambling/descrambling and cell processing on a single monolithic chip
to enable high-speed asynchronous serial data transfer between system devices. Devices can be on the same PC-
board, on separate boards connected across a backplane or connected by cables. The ORSO42G5 and
ORSO82G5 are completely pin-compatible with the ORT42G5 and ORT82G5 devices.
The ORSO42G5 and ORSO82G5 are considered pseudo-SONET devices because they do not support full over-
head processing, pointer processing or meet all SONET jitter/timing requirements. The ORSO42G5 and
ORSO82G5 are designed primarily for use as SONET backplane devices and not for network termination.
Although they format and process data as SONET frames, they cannot terminate data directly on a SONET ring
without additional functionality being implemented in the FPGA logic because the embedded core is not fully
SONET compliant on a stand-alone basis.
The ORSO42G5 and ORSO82G5 embedded cores support the following:
• Section/Line Overhead: A1/A2 (framing bytes), B1 (BIP-8), K2 (APS)
• Alarms: OOF (Out Of Frame), B1 error, RDI
• Two modes of automatic Transport OverHead (TOH) generation and insertion
• AIS-L insertion
• SPE signal generation which support +/- stuff events (but no pointer processing)
Embedded Core Overview
The functions in the embedded core portion of the ORSO42G5 and ORSO82G5 devices include:
• Eight channel 2.7 Gbps serializer/deserializer functions with Clock and Data Recovery (CDR).
• Eight-bit Interface to the Series 4 system bus for control and status information exchange.
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