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2096VE Datasheet, PDF (6/12 Pages) Lattice Semiconductor – 3.3V In-System Programmable SuperFAST™ High Density PLD | |||
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Specifications ispLSI 2096VE
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER
TEST 3
COND.
#
DESCRIPTION1
-135
-100
UNITS
MIN. MAX. MIN. MAX.
tpd1
A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass
â 7.5 â 10.0 ns
tpd2
A 2 Data Propagation Delay
â 10.0 â 13.0 ns
fmax
A
3 Clock Frequency with Internal Feedback 2
135 â 100 â MHz
fmax (Ext.)
fmax (Tog.)
â
4
Clock
Frequency
with
External
Feedback
(1
tsu2 +
) tco1
â 5 Clock Frequency, Max. Toggle
100 â 77 â MHz
143 â 100 â MHz
tsu1
â 6 GLB Reg. Setup Time before Clock, 4 PT Bypass
5.0 â 6.5 â ns
tco1
A 7 GLB Reg. Clock to Output Delay, ORP Bypass
â 4.0 â 5.0 ns
th1
â 8 GLB Reg. Hold Time after Clock, 4 PT Bypass
0.0 â 0.0 â ns
tsu2
â 9 GLB Reg. Setup Time before Clock
6.0 â 8.0 â ns
tco2
A 10 GLB Reg. Clock to Output Delay
â 5.0 â 6.0 ns
th2
â 11 GLB Reg. Hold Time after Clock
0.0 â 0.0 â ns
tr1
A 12 Ext. Reset Pin to Output Delay
â 10.0 â 13.5 ns
trw1
â 13 Ext. Reset Pulse Duration
5.0 â 6.5 â ns
tptoeen
B 14 Input to Output Enable
â 12.0 â 15.0 ns
tptoedis
C 15 Input to Output Disable
â 12.0 â 15.0 ns
tgoeen
B 16 Global OE Output Enable
â 7.0 â 9.0 ns
tgoedis
C 17 Global OE Output Disable
â 7.0 â 9.0 ns
twh
â 18 External Synchronous Clock Pulse Duration, High
3.5 â 5.0 â ns
twl
â 19 External Synchronous Clock Pulse Duration, Low
3.5 â 5.0 â ns
1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock.
2. Standard 16-bit counter using GRP feedback.
3. Reference Switching Test Conditions section.
Table 2-0030B/2096VE
6
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