I0198 Datasheet, PDF (4/4 Pages) Lattice Semiconductor – Build Leading Edge Systems with Proven 3rd Generation FPGAs

Design Made Simple with Advanced Design Software and IP
Lattice Diamond Design Software
Lattice Diamond^® design software offers leading-edge design and
implementation tools optimized for cost sensitive, low-power Lattice
FPGA architectures. Diamond is the next generation replacement
for ispLEVER^® featuring design exploration, ease of use, improved
design flow, and numerous other enhancements. The combination
of new and enhanced features allows users to complete designs
faster, easier, and with better results than ever before.
Intellectual Property
Lattice offers an expanding portfolio of IP cores (LatticeCORE^™) to
support the easy integration of commonly used functions. Lattice
also offers IP Suites that are a collection of related IP cores for
select applications/markets at very attractive prices. The following
table provides a partial listing of IP Suites available for the
LatticeECP3 family. In addition to these, Lat­ticeCORE Connections
Partners also offer a wide range of IP. For a complete list of IP
options, please visit www.latticesemi.com/ip.
LatticeCORE IP Suites for LatticeECP3 FPGAs
IP Suite
Value
PCI
Express
Gigbit
Ethernet
Signal
Processing
Video &
Display
Included IP Cores
• DDR3/DDR2/DDR Memory
Controller
• FFT Compiler
• FIR Filter Generator
• Triple Speed 10/100/1G
Ethernet MAC
• PCI Express Endpoint x1 / x4
• PCI Express Root Complex
Lite x1 / x4
• PCI Target 32-bit / 64-bit
• PCI Master/Target 32-bit /
64-bit
• Scatter Gather DMA
• 10Gb+ Ethernet MAC
• Scatter Gather DMA
• SGMII & Gigabit Ethernet
MAC
• Triple Speed 10/100/1G
Ethernet MAC
• XAUI
• Advanced FIR Filter
• Block Convolutional Encoder
• Block Viterbi Decoder
• Cascaded Integrated Comb
Filter - CIC
• CORDIC
• Correlator
• Distributed Arithmetic FIR
Filter
• Dynamic Block Reed Solomon
Decoder / Encoder
• FFT Compiler
• FIR Filter Generator
• Interleaver / De-interleaver
• Numerically Controlled
Oscillator
• Turbo Decoder / Encoder
• 2D FIR Filter
• Color Space Converter
• Edge Detector
• Gamma Corrector
• Median Filter
• Tri-rate SDI PHY
• Scaler
LatticeECP3 (Economy Plus FPGAs with SERDES, sysDSP Blocks, & Source Synchronous I/O)
Parameter
LUTs (K)
Number of EBR SRAM Blocks
EBR Block SRAM (K bits)
Distributed RAM (K bits)
18x18 Embedded Multipliers
3.2Gbps SERDES Channels
Maximum Available I/O
Number of PLLs/DLLs
Power Grades¹
Speed Grades²
Packages & SERDES / I/O Combinations
328-ball csBGA (10 x 10 mm)
256-ball ftBGA (17 x 17 mm)
484-ball fpBGA (23 x 23 mm)
672-ball fpBGA (27 x 27 mm)
1156-ball fpBGA (35 x 35 mm)
1. -S = Standard Power; -L = Low Power
2. -9 = High-Speed Device
ECP3-17
17
38
700
36
24
4
222
2+2
-S, -L
-6, -7, -8
2/116
4/133
4/222
ECP3-35
33
72
1327
68
64
4
310
4+2
-S, -L
-6, -7, -8, -9
ECP3-70
67
240
4420
145
128
12
490
10+2
-S, -L
-6, -7, -8, -9
ECP3-95
92
240
4420
188
128
12
490
10+2
-S, -L
-6, -7, -8, -9
ECP3-150
149
372
6850
303
320
16
586
10+2
-S, -L
-6, -7, -8, -9
4/133
4/295
4/310
4/295
8/380
12/490
4/295
8/380
12/490
8/380
16/586
Applications Support
1-800-LATTICE (528-8423)
503-268-8001
[e-mail]
Copyright © 2012 Lattice Semiconductor Corporation. Lattice Semiconductor, L (stylized) Lattice Semiconductor Corp., and Lattice (design), ispLEVER, ispLeverCORE, Lattice Diamond, LatticeCORE,
LatticeECP3, LatticeECP2M, LatticeMico32, sysCLOCK, sysCONFIG, sysDSP, sysIO, sysMEM, and TransFR are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United
States and/or other countries. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
May 2012
Order #: I0198H
LATTICESEMI.COM