I0198 Datasheet, PDF (3/4 Pages) Lattice Semiconductor – Build Leading Edge Systems with Proven 3rd Generation FPGAs

High-Value, Low-Power Serial
Protocol Solutions
LatticeECP3 Multi-Protocol Stack
Supports commonly used Ethernet protocols (1GbE, SGMII, and XAUI),
Wireless protocols, such as CPRI, are supported by extension
Supports PCI Express and Serial RapidIO
Supported
PHYs
GbE / SGMII*
XAUI
PCI
Express
Serial
RapidIO
Soft IP
Embedded
SERDES
and
Physical
Coding
Sub-Layers
(PCS)
GbE & SGMII
State Machine
Auto Negotiation
Clock Tolerance
Compensation
8b/10b
Rx Link
Synchronize
XAUI PCS
Soft Logic
XAUI State
Machine
Clock Tolerance
Compensation
Channel
Alignment
8b/10b
Rx Link
Synchronize
PCIe PHY
Soft Logic
Framing
LTSSM
Clock Tolerance
Compensation
Channel
Alignment
8b/10b
Rx Link
Synchronize
State Machine
Soft Logic
RX State
Machine
Clock Tolerance
Compensation
Channel
Alignment
8b/10b
Rx Link
Synchronize
Tx Rx
* CPRI Supported By Extension
Tx Rx
Tx Rx
LatticeECP3 SERDES
Tx Rx
CPRI Low Latency Option
Supports data rates for up to 3.072Gbps CPRI links
Supports multi-hop RRH applications through innovative low-latency
variation SERDES implemementation
Library of CPRI, JESD204A, SRIO, Ethernet and DSP cores and reference
designs for single-chip RF and baseband implementations
SERDES/PCS
Recovered Clock
FPGA Fabric
ff_rxi_clk
rx_clk
RX
CDR Des
WA
10b/8b
Bypassable
Bridge
FIFO
8b or 16b
rx data
CPRI
IP Core
Offset
To SCI
IP Core
User Interface
Word Aligner Variation
Reported in
Offset Registers
Bypassable Bridge FIFO
for Single Clock
Domain Implementation
Enhanced SMPTE Support
Any rate, any channel, any direction for SD/HD and 3G
• New x11 divider setting
• Added independent Rx clocking per channel
Truly independent Rx/Tx multi-rate support for SD/HD/3G!
HD
3G 3G
148.35 MHz
HD ^{148.5 MHz}
148.5 MHz _SD
HD
3G Fractional SD
Reference Clock Reference Clock
Rx
Tx
Tx 3
Rx 3
Rec Clk 3
Tx 2
Rx 2
Rec Clk 2
PLL (x20)
SMPTE Divider Settings
DIV1: 2.97 Gbps
DIV2: 1.485 Gbps
DIV11: 270 Mbps
Fabric
Tx 1
Rx 1
Rec Clk 1
Tx 0
Rx 0
Rec Clk 0
Evaluation &
Development
Boards
To accelerate your design development,
Lattice offers several development boards
to support LatticeECP3 designs. These
boards enable you to evaluate the benefits
and capabilities of LatticeECP3 devices in
a lab setting.
The LatticeECP3 Versa Evaluation Board
is the industry's lowest cost FPGA board
with PCI Express and two Gigabit Ethernet
ports. It is useful for appreciating the quality
of LatticeECP3 SERDES and developing a
wide-range of networking and system design
applications.
The Lattice HDR-60 Video Camera
Development Kit is an FPGA-based HDR
camera capable of supporting 1080p60
over HDMI/DVI output. The design needs
no external frame buffer, enabling the lowest
cost FPGA HDR camera BOM. Features include
Auto White Balance, industry's fastest
auto-exposure, extremely low-latency and
120dB High Dynamic Range.
The LatticeECP3 Serial Protocol Board provides
a platform to evaluate the LatticeECP3 device's
multi-protocol serial protocol functionality as well
as DDR2 and DDR3 memory interfaces.
The LatticeECP3 Video Protocol Board provides
a platform to evaluate the LatticeECP3 device's
multi-rate 3G/HD/SDI and 7:1 LVDS capabilities.
Breakout options for other display interfaces are
also available.