I0198 Datasheet, PDF (2/4 Pages) Lattice Semiconductor – Build Leading Edge Systems with Proven 3rd Generation FPGAs

LatticeECP3 Architecture
Architecture Overview
LatticeECP3 Block Diagram
LatticeECP3 FPGAs utilize Lattice’s third generation of cost
optimized transceivers and a low-power 65-nm process FPGA
architecture. Building on the successful LatticeECP2M^™ FPGA
family, LatticeECP3 devices deliver high-performance SERDES
blocks, cascadable high-performance sysDSP^™, ultra-high logic
and sysMEM^™ embedded RAM, distributed memory, sysCLOCK
PLLs, DDR3 memory interface, and sysIO buffers. LatticeECP3
provides a low-cost, low-power programmable solution for a
wide variety of wireless and wireline applications.
Programmable Function
Unit (PFU) Block Diagram
Carry Chain
Embedded 3.2Gbps SERDES
support PCI Express, Ethernet
(XAUI, 1GbE, SGMII), CPRI,
and 3G/HD/SD-SDI.
Pre-Engineered Source
Synchronous Support
implements DDR3 at
800Mbps and generic
interfaces up to 1Gbps.
Programmable
Function Unit
(PFU)
perform Logic,
Arithmetic,
Distributed RAM
and Distributed
ROM functions.
sysCLOCK PLLs
& DLLs for
clock
management.
SERDES SERDES SERDES SERDES
Cascadable
sysDSP Blocks
implements
high-performance
multiplier, MAC,
wide adder
trees, and ALU
functions
efficiently.
Slice 3
LUT4
LUT4
Slice 2
LUT4
FF
Flexible sysIO
Buffers support
LVCMOS,
HSTL, SSTL,
LVDS and more.
On-Chip
Oscillator
Configuration Logic supports
dual boot, encryption and TransFR
updates.
JTAG
sysMEM Embedded Block
RAM (EBR) provides 18kbit
dual port RAM.
From
Routing
LUT4
LUT4
LUT4
LUT4
FF
Slice 1
To
Routing
FF
FF
Slice 0
FF
sysMEM Config Options
Single Port
16384 x 1
8192 x 2
4096 x 4
2048 x 9
1024 x 18
512 x 36
Dual Port
16384 x 1
8192 x 2
4096 x 4
2048 x 9
1024 x 18
—
Pseudo-Dual
Port
16384 x 1
8192 x 2
4096 x 4
2048 x 9
1024 x 18
512 x 36
Dual-boot and 128-bit AES
Encryption
SPI Configuration
Memory
LatticeECP3
[ ^{Sector 0}
[ ^{Sector 1}
Configuration A
Configuration B
Read
Data
Decryption
Engine
FPGA
Logic
Control ^{128-bit Key}
LUT4
FF
Carry Chain
sysDSP Block Diagram
Slice 0
Input Registers
Slice 1
Input Registers
Multipliers
Pipeline
Registers
ALU
∑±&+⊕
==
Output Registers
Multipliers
Pipeline
Registers
ALU
∑±&+⊕
==
Output Registers
LatticeECP3 EBR SRAM (Mbits)
7
6
5
4
3
2
1
0
17K
UP TO
7Mb
33K
67K
LUTs
92K 149K
sysCLOCK PLL Block Diagram
Control
Signals
Clock
Input
Clock
Feedback
Phase
Frequency
Detector /
Voltage
Control
Oscillator
÷3
Phase/
Duty Cycle/
Duty Trim
Duty Trim
Pre-Engineered Source
Synchronous Interfaces
DDR3 (800 Mbps)
7:1 LVDS, ADC/DAC
FPGA
Fabric
4:1
Gearbox
Tri-State
Register Block
(2 Flip/Flops)
Output Register
Block
(6 Flip/Flops)
ISI
Correction
4:1
Gearbox
Input Register
Block
(15 Flip/Flops)
DQS/Strobe Delay & Transition Detect
& Write Clock Generation
Internal Feedback
Reset
Divider
Lock Detect