I0198 Datasheet, PDF (1/4 Pages) Lattice Semiconductor – Build Leading Edge Systems with Proven 3rd Generation FPGAs

LOW-POWER SERDES, HIGH-SPEED DDR3, HIGH-CALIBER DSP
LatticeECP3 Family
Build Leading Edge Systems with
Proven 3rd Generation FPGAs
LatticeECP3^™ is the best-in-class mid-range FPGA with high-
performance SERDES, full-featured DSP blocks, and support for
state-of-the-art memory interfaces including DDR3. It offers 35%
to 100% more silicon resources in smaller packages compared
to competitors. Low-power LatticeECP3 FPGAs are used in
a wide range of applications, such as wireless and wireline
communication, video processing, security and surveillance,
industrial networking, industrial automation, computing, storage,
medical equipment, and consumer.
LatticeECP3 FPGAs offer up to 150K LUTs of logic capacity
and 7 Mbits of memory for system integration, cascadable high-
performance DSP blocks for signal processing, high-speed memory
interfaces including DDR3 at 800 Mbps, and up to 1 Gbps LVDS
performance for ADC/DAC and SPI4.2 interfaces. LatticeECP3
further enables you to build high-speed systems with proven 3.2
Gbps low-power SERDES qualified for a number of protocols – PCI
Express 1.1, Ethernet (GbE, SGMII & XAUI), SMPTE SDI (3G/HD/
SD), Serial RapidIO 2.1, low-latency CPRI, and JESD204A.
To accelerate design of LatticeECP3 powered systems, Lattice also
offers a number of generic and application-specific development
kits, an expanding portfolio of free readymade reference designs,
and a set of economical IP suites.
FPGA Fabric Features and Capabilities
Low-Power, High-Value FPGA Fabric
• Low-power 65nm process with 4-input look-up table (LUT)
fabric
• Logic densities from 17K to 149K LUTs
• Up to 7Mbits of Embedded Block RAM (EBR) and 303Kbits of
distributed RAM
High-Speed Embedded SERDES
• Up to 16 channels with data rates from 150Mbps to 3.2Gbps
• Less than 110mW power per channel at 3.2Gbps
• Supports PCI Express, Ethernet (GbE, XAUI, SGMII),
SMPTE, Serial RapidIO 2.1, CPRI
Flexible sysIO^™ Buffers
• LVCMOS 33/25/18/15/12, PCI
• SSTL 33/25/18/15 & HSTL15 & HSTL18
• LVDS, Bus-LVDS, RSDS, MLVDS & LVPECL
• 800Mbps DDR3
• Up to 1Gbps LVDS
Wide Range of Package & User I/O Options
• Up to 586 user I/O pins
• Proven low-cost wirebond fpBGA packages
• Density migration across all densities
• Pb-free / RoHS-compliant
sysCLOCK^™ PLL and DLL
• 2 DLLs per device, 2 to 10 PLLs per device
LatticeECP3 Features and Benefits
Embedded SERDES
3.2Gbps operation with less than 110mW power per
channel
Built-in pre-emphasis and equalization
Supports PCIe, Ethernet (GbE, XAUI, & SGMII), SMPTE,
Serial RapidIO, CPRI and JESD204A
Quad-based architecture with mix and match of different
protocols within a quad
Single-channel granularity for 3G/HD/SD SDI
Support low latency variation CPRI links for multi-hop
RRH applications
Cascadable DSP with ALU
Fully cascadable slice for high performance filter and
wide arithmetic functions
Implement rounding and truncation functions with 54-bit
cascadable arithmetic logic unit
Multiply, accumulate, addition and subtraction
Up to 320 18x18 multipliers
High-Speed I/O
Pre-engineered DDR3 memory (800Mbps)
Up to 1Gbps LVDS
ADC/DAC, 7:1 LVDS, XGMII
Advanced Configuration Options
Configure with SPI boot flash or parallel burst mode flash
Protect your designs with 128-bit AES
Dual-boot provides backup configuration copy
TransFR^™ I/O support updates while system operates
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