1048EA Datasheet, PDF (3/14 Pages) Lattice Semiconductor – In-System Programmable High Density PLD

Specifications ispLSI 1048EA
Boundary Scan
Figure 2. Boundary Scan Waveforms and Timing Specifications
TMS
TDI
TCK
T_btch
T_btsu
T_btcl
T_bth
T_btcp
TDO
Data to be
captured
Data to be
driven out
T_btvo
T_btco
Valid Data
T_btcpsu
T_btcph
Data Captured
T_btuov
T_btuco
Valid Data
T_btoz
Valid Data
T_btuoz
Valid Data
Symbol
t_btcp
t_btch
tbtcl
tbtsu
tbth
trf
tbtco
tbtoz
tbtvo
tbtcpsu
tbtcph
tbtuco
tbtuoz
tbtuov
Parameter
TCK [BSCAN test] clock pulse width
TCK [BSCAN test] pulse width high
TCK [BSCAN test] pulse width low
TCK [BSCAN test] setup time
TCK [BSCAN test] hold time
TCK [BSCAN test] rise and fall time
TAP controller falling edge of clock to valid output
TAP controller falling edge of clock to data output disable
TAP controller falling edge of clock to data output enable
BSCAN test Capture register setup time
BSCAN test Capture register hold time
BSCAN test Update reg, falling edge of clock to valid output
BSCAN test Update reg, falling edge of clock to output disable
BSCAN test Update reg, falling edge of clock to output enable
Min Max Units
100 –
ns
50
–
ns
50
–
ns
20
–
ns
25
–
ns
50
– mV/ns
–
25 ns
–
25 ns
–
25 ns
40
–
ns
25
–
ns
–
50 ns
–
50 ns
–
50 ns
3