1048EA Datasheet, PDF (10/14 Pages) Lattice Semiconductor – In-System Programmable High Density PLD

Specifications ispLSI 1048EA
Maximum GRP Delay vs. GLB Loads
5
4
3
ispLSI 1048EA-100
ispLSI 1048EA-125
ispLSI 1048EA-170
2
1
14 8
16
32
48
GLB Load GRP/GLB/1048EA
Power Consumption
Power consumption in the ispLSI 1048EA device de-
pends on two primary factors: the speed at which the
device is operating and the number of Product Terms
used. Figure 4 shows the relationship between power
and operating speed.
Figure 4. Typical Device Power Consumption vs fmax
500
ispLSI 1048EA
400
300
200
100
0 25 50 75 100 125 150 175
fmax (MHz)
Notes: Configuration of twelve 16-bit counters, Typical current at 5V, 25¡C
Icc can be estimated for the ispLSI 1048EA using the following equation:
Icc = 20mA + (# of PTs * .45) + (# of nets * Max Freq * .0087)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The Icc estimate is based on typical conditions (Vcc = 5.0V, room temperature) and an assumption of four GLB
loads on average exists. These values are for estimates only. Since the value of Icc is sensitive to operating
conditions and the program in the device, the actual Icc should be verified.
0127/1048EA
Package Thermal Characteristics
For the ispLSI 1048EA-170, it is strongly recommended
that the actual Icc be verified to ensure that the maximum
junction temperature (T_J) with power supplied is not
exceeded. Depending on the specific logic design and
clock speed, airflow may be required to satisfy the maxi-
mum allowable junction temperature (T_J) specification.
Please refer to the Thermal Management section of the
Lattice Semiconductor Data Book or CD-ROM for addi-
tional information on calculating T_J.
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