1048EA Datasheet, PDF (11/14 Pages) Lattice Semiconductor – In-System Programmable High Density PLD

Specifications ispLSI 1048EA
Pin Description
NAME
I/O 0 - I/O 5
I/O 6 - I/O 11
I/O 12 - I/O 17
I/O 18 - I/O 23
I/O 24 - I/O 29
I/O 30 - I/O 35
I/O 36 - I/O 41
I/O 42 - I/O 47
I/O 48 - I/O 53
I/O 54 - I/O 59
I/O 60 - I/O 65
I/O 66 - I/O 71
I/O 72 - I/O 77
I/O 78 - I/O 83
I/O 84 - I/O 89
I/O 90 - I/O 95
PQFP / TQFP PIN NUMBERS
DESCRIPTION
21, 22,
27, 28,
34, 35,
40, 41,
52, 53,
58, 59,
66, 67,
72, 73,
85, 86,
91, 92,
98, 99,
104, 105,
117, 118,
123, 124,
2, 3,
8, 9,
23, 24,
29, 30,
36, 37,
42, 43,
54, 55,
60, 61,
68, 69,
74, 75,
87, 88,
93, 94,
100, 101,
106, 107,
119, 120,
125, 126,
4,
5,
10, 11,
25, 26, Input/Output Pins - These are the general purpose I/O pins used by the
31, 32, logic array.
38, 39,
44, 45,
56, 57,
62, 63,
70, 71,
76, 77,
89, 90,
95, 96,
102, 103,
108, 109,
121, 122,
127, 128,
6,
7,
12, 13
GOE0, GOE1
64, 114
IN 2, IN 4, IN 6-IN 11 47, 51
116, 14
Global Output Enable input pins.
84, 110, 111, 115, Dedicated input pins to the device.
TDI
20
TMS
46
TDO
50
TCK
78
Input - Functions as an input pin to load programming data into the
device and also is used as one of the two control pins for the ISP JTAG
state machine.
Input - Controls the operation of the ISP JTAG state machine.
Output - Functions as an output pin to read serial shift register data.
Input - Functions as a clock pin for the Serial Shift Register.
RESET
Y0
Y1
Y2
Y3
GND
VCC
VCCIO
19
Active Low (0) Reset pin which resets all of the GLB and I/O registers in
the device.
15
Dedicated Clock input. This clock input is connected to one of the clock
inputs of all of the GLBs on the device.
83
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB on the
device.
80
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any GLB and/or
any I/O cell on the device.
79
Dedicated Clock input. This clock input is brought into the clock
distribution network, and can optionally be routed to any I/O cell on the
device.
1, 17, 33, 49,
97, 112
65, 81, Ground (GND)
16, 48, 82, 113
V_CC
18
Supply voltage for output drivers, 5V or 3.3V.
Table 2-0002C/1048EA
11