GAL16V8 Datasheet, PDF (16/22 Pages) Lattice Semiconductor – High Performance E2CMOS PLD Generic Array Logic

Power-Up Reset
Specifications GAL16V8
Vcc (min.)
Vcc
CLK
tpr
INTERNAL REGISTER
Q - OUTPUT
tsu
t wl
Internal Register
Reset to Logic "0"
FEEDBACK/EXTERNAL
OUTPUT REGISTER
Device Pin
Reset to Logic "1"
Circuitry within the GAL16V8 provides a reset signal to all reg-
isters during power-up. All internal registers will have their Q
outputs set low after a specified time (tpr, 1µs MAX). As a result,
the state on the registered output pins (if they are enabled) will
always be high on power-up, regardless of the programmed
polarity of the output pins. This feature can greatly simplify state
machine design by providing a known state on power-up. Be-
cause of the asynchronous nature of system power-up, some
conditions must be met to provide a valid power-up reset of the
device. First, the VCC rise must be monotonic. Second, the clock
input must be at static TTL level as shown in the diagram during
power up. The registers will reset within a maximum of tpr time.
As in normal system operation, avoid clocking the device until all
input and feedback path setup times have been met. The clock
must also meet the minimum pulse width requirements.
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PIN
Vcc
Active Pull-up
Circuit
Vcc Vref Vcc
ESD
Protection
Circuit
PIN
Feedback
Tri-State
Control
Active Pull-up
Circuit
Vcc
Vref
PIN
ESD
Protection
Circuit
Typ. Vref = 3.2V
Typical Input
Data
Output
PIN
Typ. Vref = 3.2V
Feedback
(To Input Buffer)
Typical Output
16