813N252DI-02 Datasheet, PDF (8/23 Pages) Integrated Device Technology – Jitter Attenuator & FemtoClock NG Multiplier

813N252DI-02 DATA SHEET
AC Electrical Characteristics
Table 5. AC Characteristics, V_CC = V_CCO = V_CCX = 3.3V ± 5%, T_A = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
f_IN
f_OUT
tjit(Ø)
Input Frequency
Output Frequency
RMS Phase Jitter, (Random),
NOTE 1
125MHz f_OUT, 27MHz crystal,
Integration Range: 12kHz – 20MHz
156.25MHz f_OUT, 27MHz crystal,
Integration Range: 12kHz – 20MHz
0.008
25
PSNR
Power Supply Noise Rejection;
NOTE 2
V_PP = 50mV Sine Wave,
Range: 10kHz – 10MHz
tsk(o)
Output Skew; NOTE 3, 4
t_R / t_F
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
150
48
t_LOCK
Output-to-Input Phase
Lock Time; NOTE 5
Reference Clock Input is ±100ppm from
Nominal Frequency
Typical
0.65
0.6
-85
4
Maximum
155.52
312.5
Units
MHz
MHz
ps
ps
dB
80
ps
450
ps
52
%
s
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: Characterized with outputs at the same frequency using the loop filter components for the 35Hz loop bandwidth.
Refer to Jitter Attenuator Loop Bandwidth Selection Table.
NOTE 1: Refer to the Phase Noise Plot.
NOTE 2: PSNR results achieved by injecting noise on V_CCA supply pin with no external filter network.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 5: Lock Time measured from power-up to stable output frequency.
REVISION 1 08/14/15
8
JITTER ATTENUATOR & FEMTOCLOCK NG^® MULTIPLIER