813N252DI-02 Datasheet, PDF (12/23 Pages) Integrated Device Technology – Jitter Attenuator & FemtoClock NG Multiplier

813N252DI-02 DATA SHEET
3.3V Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, HCSL and other
differential signals. Both differential inputs must meet the V_PP and
V_CMR input requirements. Figures 2A to 2E show interface examples
for the CLK /nCLK input driven by the most common driver types. The
input interfaces suggested here are examples only. Please consult
with the vendor of the driver component to confirm the driver
termination requirements. For example, in Figure 2A, the input
termination applies for IDT open emitter LVHSTL drivers. If you are
using an LVHSTL driver from another vendor, use their termination
recommendation.
1.8V
Zo = 50Ω
Zo = 50Ω
LVHSTL
IDT
LVHSTL Driver
3.3V
CLK
R1
R2
50Ω
50Ω
nCLK
Differential
Input
Figure 2A. CLK/nCLK Input Driven by an
IDT Open Emitter LVHSTL Driver
Figure 2B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 2C. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 2D. CLK/nCLK Input Driven by a
3.3V LVDS Driver
3.3V
3.3V
*R3 33Ω
Zo = 50Ω
Zo = 50Ω
*R4 33Ω
HCSL
R1
50Ω
*Optional – R3 and R4 can be 0Ω
CLK
nCLK
R2
50Ω
Differential
Input
Figure 2E. CLK/nCLK Input Driven by an HCSL Driver
REVISION 1 08/14/15
12
JITTER ATTENUATOR & FEMTOCLOCK NG^® MULTIPLIER