813N252DI-02 Datasheet, PDF (17/23 Pages) Integrated Device Technology – Jitter Attenuator & FemtoClock NG Multiplier

813N252DI-02 DATA SHEET
Zo = 50
Zo = 50
LVPECL Driv er
VCC
R5
R6
125
125
Zo = 50
Zo = 50
CLK0
nCLK0
LVPECL Driv er
R7
R8
84
85
VCC
R1
R2
125
125
CLK1
nCLK1
R20
R4
84
84
Logic Control Input Examples
Set Logic
VCC _{Input to}
'1'
RU1
1K
Set Logic
VCC _{Input to}
'0'
RU2
Not Install
To Logic
Input
pins
RD1
Not Install
To Logic
Input
pins
RD2
1K
3-pole loop filter example - (optional)
R3
LF
LF
Rs
820k
365k
Cs
1uF
Cp
0.002uF
C3
220pF
C1
TUNE
C2
TUNE
XTAL_OUT
27MHz
1 0 p F ^X1
XTAL_IN
R11 10
VCC
VCCX
C4
0.1u
C5
10u
2-pole loop filter for Mid Bandwidth setting
LF
Rs
365k
Cs
1uF
LF
VCC
Cp
0.002uF
CLK_SEL
R14
C7
1.5K
0.1u
U1
1
2 ^LF1
3
4
5
LF0
ISET
VEE
6 ^CLK_SEL
7
8
VCC
RESERVED
VEE
3.3V
BLM18BB221SN1
1
2
Ferrite Bead C6
C5
0.1uF
10uF
VCC
C11
0.1u
VCCO
0.1u
C6
24
VEE ₂₃
nQB
QB
VCCO
22
21
20
nQA ₁₉
QA
VEE
ODASEL_0
18
17
nQB
QB
nQA
QA
ODASEL_0
3.3V
BLM18BB221SN1
1
2
Ferrite Bead
C6
C5
0.1uF
VCC
C8
10uF 0.1u
R19
VCCA 10
VCC
C9
C10
0.1u
10u
3.3V
R9
133
Zo = 50 Ohm
R10
133
+
Zo = 50 Ohm
-
R12
R13
82.5
82.5
LVPECL
Termination
Zo = 50 Ohm
Zo = 50 Ohm
+
-
R15
R16
50
50
LVPECL
R18
50
Optional
Y-Termination
Figure 5. 813N252DI-02 Schematic Example
JITTER ATTENUATOR & FEMTOCLOCK NG^® MULTIPLIER
17
REVISION 1 08/14/15