CPC7695 Datasheet, PDF (16/25 Pages) Clare, Inc. – Line Card Access Switch

INTEGRATED CIRCUITS DIVISION
CPC7695
2. Functional Description
2.1 Introduction
The CPC7695 has the following states:
• Talk. Loop break switches SW1 and SW2 closed, all
other switches open.
• Ringing. Ringing switches SW3 and SW4 closed, all
other switches open.
• TESTout. Testout switches SW5 and SW6 closed,
all other switches open.
• Ringing generator test. SW7 and SW8 closed, all
other switches open.
• TESTin. Testin switches SW9 and SW10 closed, all
other switches open.
• Simultaneous TESTin and TESTout. SW9, SW10,
SW5, and SW6 closed, all other switches open.
• Simultaneous TESTout and Ringing generator
test. SW5, SW6, SW7, and SW8 closed, all other
switches open (only on the xC and xD versions).
• All-Off. All switches open.
See “Truth Tables” on page 15 for more information.
The CPC7695 offers break-before-make and
make-before-break switching from the Ringing state to
theTalk state with simple TTL level logic input control.
Solid-state switch construction means no impulse
noise is generated when switching during ringing
cadence or ring trip, eliminating the need for external
zero-cross switching circuitry. State-control is via TTL
logic-level input so no additional driver circuitry is
required. The linear line break switches SW1 and
SW2 have exceptionally low R_ON and excellent
matching characteristics. The ringing switch, SW4,
has a minimum open contact breakdown voltage of
465V at +25°C, sufficiently high with proper protection
to prevent breakdown in the presence of a transient
fault condition (i.e., prevent passing the transient on to
the ringing generator).
Integrated into the CPC7695 is an over-voltage
clamping circuit, active current limiting, and a thermal
shutdown mechanism to provide protection to the
SLIC during a fault condition. Positive and negative
lightning surge currents are reduced by the current
limiting circuitry and hazardous potentials are diverted
away from the SLIC via the protection diode bridge or
the optional integrated protection SCR. Power-cross
potentials are also reduced by the current limiting and
thermal shutdown circuits.
To protect the CPC7695 from an overvoltage fault
condition, the use of a secondary protector is required.
The secondary protector must limit the voltage seen at
the T_LINE and R_LINE terminals to a level below the
maximum breakdown voltage of the switches. To
minimize the stress on the solid-state contacts, use of
a foldback or crowbar type secondary protector is
highly recommended. With proper selection of the
secondary protector, a line card using the CPC7695
will meet all relevant ITU, LSSGR, TIA/EIA and IEC
protection requirements.
The CPC7695 operates from a single +5V supply only.
This gives the device extremely low idle and active
power consumption with virtually any range of battery
voltage. The battery voltage used by the CPC7695
has a two fold function. For protection purposes it is
used as a fault condition current source by the internal
integrated protection circuitry. Secondly, it is used as a
reference so that in the event of battery voltage loss,
the CPC7695 will enter the All-Off state.
2.2 Start-up
The CPC7695 uses smart logic to monitor the V_DD
supply. Any time V_DD is below an internally set
threshold, the smart logic places the control logic into
the All-Off state. An internal pullup on the LATCH pin
locks the CPC7695 in the All-Off state following
start-up until the LATCH pin is pulled down to a logic
low. Prior to the assertion of a logic low at the LATCH
pin, the switch control inputs must be properly
conditioned.
2.3 Data Latch
The CPC7695 has an integrated transparent data
latch. Operation of the latch enable is controlled by
TTL logic input levels at the LATCH pin. Data input to
the latch are via the input pins, while the output of the
data latch are internal nodes used for state control.
When the LATCH enable control pin is at logic 0 the
data latch is transparent and the input data control
signals flow directly through the latch to the state
control circuitry. A change in input will be reflected by a
change in switch state. Whenever the LATCH enable
control pin is at logic 1, the latch is active and data is
locked. Subsequent input changes will not result in a
change to the control logic or affect the existing switch
state.
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