IS62WV12816EALL Datasheet, PDF (9/17 Pages) Integrated Silicon Solution, Inc – Three state outputs

IS62/65WV12816EALL
IS62/65WV12816EBLL
TIMING DIAGRAM
READ CYCLE NO. 1^(1,2) (ADDRESS CONTROLLED) (
= =VIL, CS2#= =VIH)
ADDRESS
I/O0-15
tRC
tOHA
PREVIOUS DATA VALID
tAA
Low-Z
tOHA
DATA VALID
Low-Z
READ CYCLE NO. 2^(1,3) (
ADDRESS
, CS2,
, AND
&
tRC
CONTROLLED)
tAA
tOHA
CS2
,
I/O0-15
tDOE
tLZOE
tACS1/tACS2
tLZCS1/
tLZCS2
tBA
tLZB
HIGH-Z
LOW-Z
tHZOE
tHZCS1/
tHZCS2
tHZB
DATA VALID
Notes:
1.
is HIGH for Read Cycle.
2. The device is continuously selected. ,
3. Address is valid prior to or coincident with
, , or =VIL.CS2= =VIH#.
LOW and CS2 HIGH transition.
Integrated Silicon Solution, Inc.- www.issi.com
9
Rev. 0B
12/9/2014