IS62WV10248EALL Datasheet, PDF (9/15 Pages) Integrated Silicon Solution, Inc – Data control for upper and lower bytes

IS62WV10248EALL/BLL
IS65WV10248EALL/BLL
TIMING DIAGRAM
READ CYCLE NO. 1^(1,2) (ADDRESS CONTROLLED) (
= =V_IL, CS2= =V_IH)
ADDRESS
I/O0-15
tRC
tOHA
PREVIOUS DATA VALID
tAA
Low-Z
tOHA
DATA VALID
Low-Z
READ CYCLE NO. 2^(1,3) ( , CS2, AND CONTROLLED)
Notes:
1. is HIGH for a Read Cycle.
2. The device is continuously selected. ,
3. Address is valid prior to or coincident with
= Vil. CS2= =VIH.
LOW and CS2 HIGH transition.
Integrated Silicon Solution, Inc.- www.issi.com
9
Rev. B
10/21/2014