IS62WV10248EALL Datasheet, PDF (3/15 Pages) Integrated Silicon Solution, Inc – Data control for upper and lower bytes

IS62WV10248EALL/BLL
IS65WV10248EALL/BLL
FUNCTION DESCRIPTION
SRAM is one of random access memories. Each byte has an address and can be accessed randomly. SRAM has three
different modes supported. Each function is described below with Truth Table.
STANDBY MODE
Device enters standby mode when deselected ( HIGH or CS2 LOW). The input and output pins (I/O0-7) are placed
in a high impedance state. The current consumption in this mode will be either ISB1 or ISB2 depending on the input
level. CMOS input in this mode will maximize saving power.
WRITE MODE
Write operation issues with Chip selected ( LOW and CS2 HIGH) and Write Enable ( ) input LOW. The input and
output pins(I/O0-7) are in data input mode. Output buffers are closed during this time even if is LOW.
READ MODE
Read operation issues with Chip selected ( LOW and CS2 HIGH) and Write Enable ( ) input HIGH. When is
LOW, output buffer turns on to make data output. Any input to I/O pins during READ mode is not permitted.
In the READ mode, output buffers can be turned off by pulling HIGH. In this mode, internal device operates as
READ but I/Os are in a high impedance state. Since device is in READ mode, active current is used.
TRUTH TABLE
Mode
CS2
I/O Operation
VDD Current
Not Selected
X
H
X
X
High-Z
ISB1, ISB2
(Power-down)
X
X
L
X
High-Z
ISB1, ISB2
Output Disabled
H
L
H
H
High-Z
Icc
Read
H
L
H
L
Dout
Icc
Write
L
L
H
X
Din
Icc
Integrated Silicon Solution, Inc.- www.issi.com
3
Rev. B
10/21/2014