IS62C25616BL Datasheet, PDF (9/13 Pages) Integrated Silicon Solution, Inc – 256K x 16 HIGH-SPEED CMOS STATIC RAM

IS62C25616BL, IS65C25616BL
WRITE CYCLE NO. 2 (OE is HIGH During Write Cycle) ^(1,2)
ADDRESS
OE
t WC
VALID ADDRESS
t HA
CE ^LOW
WE
t SA
UB, LB
DOUT
DATA UNDEFINED
DIN
t AW
t PWE1
t PBW
t HZWE
HIGH-Z
t LZWE
t SD
t HD
DATAIN VALID
UB_CEWR2.eps
WRITE CYCLE NO. 3 (OE is LOW During Write Cycle) ⁽¹⁾
ADDRESS
OE ^LOW
t WC
VALID ADDRESS
t HA
CE _LOW
WE
t SA
t AW
t PWE2
t PBW
UB, LB
DOUT
DATA UNDEFINED
t HZWE
HIGH-Z
t LZWE
t SD
t HD
DIN
DATAIN VALID
UB_CEWR3.eps
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW.All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write.The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE ≥ Vih.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
9
Rev.  A
06/28/2011