IS61QDB24M18A Datasheet, PDF (9/29 Pages) Integrated Silicon Solution, Inc – 2Mx36 and 4Mx18 configuration available

IS61QDB24M18A
IS61QDB22M36A
State Diagram
Power-Up
Read#
Read NOP
Read# Write#
Write NOP
Read
Load New Read
Address
Always
(fixed)
Read
DDR Read
Write
Load New Write
Address
Always
(fixed)
Write
DDR Write
Write#
Notes:
1. Internal burst counter is fixed as two-bit linear; that is when first address is A0+0, next internal burst addresses are A0+1.
2. Read refers to read active status with R# = LOW. Read# refers to read inactive status with R# = HIGH.
3. Write refers to write active status with W# = LOW. Write# refers to write inactive status with W# = HIGH.
4. The read and write state machines can be active simultaneously.
5. State machine control timing sequence is controlled by K.
Integrated Silicon Solution, Inc.- www.issi.com
9
Rev. A
8/7/2014