IS61QDB24M18A Datasheet, PDF (1/29 Pages) Integrated Silicon Solution, Inc – 2Mx36 and 4Mx18 configuration available

IS61QDB24M18A
IS61QDB22M36A
4Mx18, 2Mx36
72Mb QUAD (Burst 2) Synchronous SRAM
AUGUST 2014
FEATURES
 2Mx36 and 4Mx18 configuration available.
 On-chip Delay-Locked loop (DLL) for wide data valid
window.
 Separate independent read and write ports with
concurrent read and write operations.
 Synchronous pipeline read with EARLY write
operation.
 Double Data Rate (DDR) interface for read and
write input ports.
 Fixed 2-bit burst for read and write operations.
 Clock stop support.
 Two input clocks (K and K#) for address and control
registering at rising edges only.
 Two output clocks (C and C#) for data output control.
 Two echo clocks (CQ and CQ#) that are delivered
simultaneously with data.
 +1.8V core power supply and 1.5, 1.8V VDDQ, used
with 0.75, 0.9V VREF.
 HSTL input and output interface.
 Registered addresses, write and read controls, byte
writes, data in, and data outputs.
 Full data coherency.
 Boundary scan using limited set of JTAG 1149.1
functions.
 Byte write capability.
 Fine ball grid array (FBGA) package:
13mmx15mm and 15mmx17mm body size
165-ball (11 x 15) array
 Programmable impedance output drivers via 5x
user-supplied precision resistor.
DESCRIPTION
The
and
are
synchronous, high-performance CMOS static random access
memory (SRAM) devices. These SRAMs have separate I/Os,
eliminating the need for high-speed bus turnaround. The
rising edge of K clock initiates the read/write operation, and
all internal operations are self-timed. Refer to the
for a description of the
basic operations of these
SRAMs.
The input address bus operates at double data rate. The
following are registered internally on the rising edge of the K
clock:
 Read address
 Read enable
 Write enable
 Byte writes
 Data-in for early writes
The following are registered on the rising edge of the K#
clock:
 Write address
 Byte writes
 Data-in for second burst addresses
Byte writes can change with the corresponding data-in to
enable or disable writes on a per-byte basis. An internal write
buffer enables the data-ins to be registered half a cycle
earlier than the write address. The first data-in burst is
clocked at the same time as the write command signal, and
the second burst is timed to the following rising edge of the
K# clock.
During the burst read operation, the data-outs from the first
bursts are updated from output registers of the second rising
edge of the C# clock (starting 1.5 cycles later after read
command). The data-outs from the second bursts are
updated with the third rising edge of the C clock. The K and
K# clocks are used to time the data-outs whenever the C and
C# clocks are tied high.
The device is operated with a single +1.8V power supply and
is compatible with HSTL I/O interfaces.
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without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com
1
Rev. A
8/7/2014