IS61QDB24M18A Datasheet, PDF (11/29 Pages) Integrated Silicon Solution, Inc – 2Mx36 and 4Mx18 configuration available

IS61QDB24M18A
IS61QDB22M36A
x18 Write Truth Table
(Use the following table with the Timing Reference Diagram for Truth Table.)
Operation
Write Byte 0
Write Byte 1
Write All Bytes
Abort Write
Write Byte 0
Write Byte 1
Write All Bytes
Abort Write
K (t)
L→H
L→H
L→H
L→H
K# (t+0.5)
L→H
L→H
L→H
L→H
BW0#
L
H
L
H
L
H
L
H
BW1#
H
L
L
H
H
L
L
H
DB
D0-8 (t)
D9-17 (t)
D0-17 (t)
Don't Care
DB+1
D0-8 (t+0.5)
D9-17 (t+0.5)
D0-17 (t+0.5)
Don't Care
Notes:
1. Refer to the Timing Reference Diagram for Truth Table. Cycle time starts at n and is referenced to the K clock.
2. For all cases, W# needs to be active low during the rising edge of K occurring at time t.
3. For timing definitions refer to the AC Timing Characteristics table. Signals must meet AC specifications with respect to switching clocks K and K#.
x36 Write Truth Table
(Use the following table with the Timing Reference Diagram for Truth Table.)
Operation
K (t)
K# (t+0.5)
BW0#
BW1#
BW2#
BW3#
DB
DB+1
Write Byte 0
L→H
L
H
H
H
D0-8 (t)
Write Byte 1
L→H
H
L
H
H
D9-17 (t)
Write Byte 2
L→H
H
H
L
H
D18-26 (t)
Write Byte 3
L→H
H
H
H
L
D27-35 (t)
Write All Bytes
L→H
L
L
L
L
D0-35 (t)
Abort Write
L→H
H
H
H
H
Don't Care
Write Byte 0
L→H
L
H
H
H
D0-8 (t+0.5)
Write Byte 1
L→H
H
L
H
H
D9-17 (t+0.5)
Write Byte 2
L→H
H
H
L
H
D18-26 (t+0.5)
Write Byte 3
L→H
H
H
H
L
D27-35 (t+0.5)
Write All Bytes
L→H
L
L
L
L
D0-35 (t+0.5)
Abort Write
L→H
H
H
H
H
Don't Care
Notes:
1. For all cases, W# needs to be active low during the rising edge of K occurring at time t.
2. For timing definitions refer to the AC Timing Characteristics table. Signals must meet AC specifications with respect to switching clocks K and K#.
Integrated Silicon Solution, Inc.- www.issi.com
11
Rev. A
8/7/2014