IS61QDB24M18A Datasheet, PDF (4/29 Pages) Integrated Silicon Solution, Inc – 2Mx36 and 4Mx18 configuration available

IS61QDB24M18A
IS61QDB22M36A
SRAM Features description
Block Diagram
36 (18)
D (Data-In)
Data
Register
36 (18) 36 (18)
20 (21)
Address
Address
Register
20 (21)
Write
Driver
2M x 36
(4M x 18)
Memory Array
72 (36) _Output 72 (36)
Register
R#
W#
BWx#
4 (2)
Control
Logic
36 (18)
Q (Data-out)
2
CQ, CQ#
(Echo Clocks)
K
K#
C
C#
Doff#
Clock
Generator
Select Output Control
Note: Numerical values in parentheses refer to the x18 device configuration.
Read Operations
The SRAM operates continuously in a burst-of-two mode. Read cycles are started by registering R# in active low state
at the rising edge of the K clock. A second set of clocks, C and C#, are used to control the timing to the outputs. A set
of free-running echo clocks, CQ and CQ#, are produced internally with timings identical to the data-outs. The echo
clocks can be used as data capture clocks by the receiver device.
When the C and C# clocks are connected high, then the K and K# clocks assume the function of those clocks. In this
case, the data corresponding to the first address is clocked one and half cycles later by the rising edge of the K# clock.
The data corresponding to the second burst is clocked two cycles later by the following rising edge of the K clock.
A NOP operation (R# is high) does not terminate the previous read.
Write Operations
Write operations can also be initiated at every rising edge of the K clock whenever W# is low. The write address is
provided half cycles later, registered by the rising edge of K#. Again, the write always occurs in bursts of two.
The write data is provided in an ‘early write’ mode; that is, the data-in corresponding to the first address of the burst, is
presented half cycles before the rising edge of the following K clock. The data-in corresponding to the second write
burst address follows next, registered by the rising edge of K#.
The data-in provided for writing is initially kept in write buffers. The information in these buffers is written into the array
on the third write cycle. A read cycle to the last write address produces data from the write buffers. Similarly, a read
address followed by the same write address produces the latest write data. The SRAM maintains data coherency.
Integrated Silicon Solution, Inc.- www.issi.com
4
Rev. A
8/7/2014