IS61NLP204836B Datasheet, PDF (9/39 Pages) Integrated Silicon Solution, Inc – 100 percent bus utilization

 
IS61NLP204836B/IS61NVP/NVVP204836B
IS61NLP409618B/IS61NVP/NVVP409618B 
PIN CONFIGURATION
100-Pin TQFP
NC
NC
NC
VDDQ
Vss
NC
NC
DQb
DQb
Vss
VDDQ
DQb
DQb
NC
VDD
NC
Vss
DQb
DQb
VDDQ
Vss
DQb
DQb
DQPb
NC
Vss
VDDQ
NC
NC
NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
2
79
3
78
4
77
5
76
6
75
7
74
8
73
9
72
10
71
11
70
12
69
13
68
14
67
15
66
16
65
17
64
18
63
19
62
20
61
21
60
22
59
23
58
24
57
25
56
26
55
27
54
28
53
29
52
30
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
NC
NC
VDDQ
Vss
NC
DQPa
DQa
DQa
Vss
VDDQ
DQa
DQa
Vss
NC
VDD
ZZ
DQa
DQa
VDDQ
Vss
DQa
DQa
NC
NC
Vss
VDDQ
NC
NC
NC
4M x 18
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A
Synchronous Address Inputs
CLK
Synchronous Clock
ADV
Synchronous Burst Address Advance
BWa-BWb
Synchronous Byte Write Enable
WE
Synchronous Write Enable
CKE
Synchronous Clock Enable
Vss
Ground for Core
NC
Not Connected
CE, CE2, CE2
OE
DQa-DQb
DQPa-DQPb
MODE
Vdd
Vss
Vddq
ZZ
Synchronous Chip Enable
Asynchronous Output Enable
Synchronous Data Inputs/Outputs
Synchronous Parity Data
Inputs/Outputs
Burst Sequence Selection
Power Supply
Ground for output Buffer
I/O Power Supply
Asynchronous Snooze Enable
Integrated Silicon Solution, Inc. — www.issi.com
9
Rev. A
8/4/2014