IS61NLP204836B Datasheet, PDF (17/39 Pages) Integrated Silicon Solution, Inc – 100 percent bus utilization

 
IS61NLP204836B/IS61NVP/NVVP204836B
IS61NLP409618B/IS61NVP/NVVP409618B 
READ/WRITE CYCLE SWITCHING CHARACTERISTICS⁽¹⁾ (Over Operating Range)
 
Symbol
Parameter
-250
-200
-166
Min. Max. Min. Max. Min. Max. Unit
fmax
Clock Frequency
—
250 —
200 —
166 MHz
tkc
Cycle Time
4.0 —
5
—
6
—
ns
tkh
Clock High Time
1.7 —
2
—
2.4 —
ns
tkl
Clock Low Time 1.7
1.7 —
—
2.3 —
ns
tkq
Clock Access Time
—
2.8 —
3.1 —
3.8 ns
tkqx⁽²⁾
Clock High to Output Invalid
0.8 —
1.5 —
1.5 —
ns
tkqlz^(2,3)
Clock High to Output Low-Z
0.8 —
1
—
1.5 —
ns
tkqhz^(2,3)
Clock High to Output High-Z
—
2.8 —
3.1
3.8 ns
toeq
Output Enable to Output Valid
—
2.8 —
3.1
3.8 ns
toelz^(2,3)
Output Enable to Output Low-Z
0
—
0
—
0
—
ns
toehz^(2,3)
Output Disable to Output High-Z
—
2.8 —
3.1
3.8 ns
tas
Address Setup Time
1.4 —
1.4 —
1.5 —
ns
tws
Read/Write Setup Time
1.4 —
1.4 —
1.5 —
ns
tces
Chip Enable Setup Time
1.4 —
1.4 —
1.5 —
ns
tse
Clock Enable Setup Time
1.4 —
1.4 —
1.5 —
ns
tadvs
Address Advance Setup Time
1.4 —
1.4 —
1.5 —
ns
tds
Data Setup Time
1.4 —
1.4 —
1.5 —
ns
tah
Address Hold Time 0.4 —
0.4 —
0.5 —
ns
the
Clock Enable Hold Time
0.4 —
0.4 —
0.5 —
ns
twh
Write Hold Time
0.4 —
0.4 —
0.5 —
ns
tceh
Chip Enable Hold Time
0.4 —
0.4 —
0.5 —
ns
tadvh
Address Advance Hold Time
0.4 —
0.4 —
0.5 —
ns
tdh
Data Hold Time
0.4 —
0.4 —
0.5 —
ns
tpower⁽⁴⁾
Vdd (typical) to First Access
1
—
1
—
1
—
ms
Notes:
1.  Configuration signal MODE is static and must not change during normal operation.
2.  Guaranteed but not 100% tested. This parameter is periodically sampled.
3.  Tested with load in Figure 2.
4. tpower is the time that the power needs to be supplied above Vdd (min) initially before READ or WRITE operation can be
initiated.
Integrated Silicon Solution, Inc. — www.issi.com
17
Rev. A
8/4/2014