IS61NLP204836B Datasheet, PDF (7/39 Pages) Integrated Silicon Solution, Inc – 100 percent bus utilization

 
IS61NLP204836B/IS61NVP/NVVP204836B
IS61NLP409618B/IS61NVP/NVVP409618B 
119-PIN PBGA PACKAGE CONFIGURATION
1
2
3
A
VDDQ
A
A
B
NC
CE2
A
C
NC
A
A
D
DQb
NC
VSS
E
NC
DQb
VSS
F
VDDQ
NC
VSS
G
NC
DQb
BWb
H
DQb
NC
VSS
J
VDDQ
VDD
NC
K
NC
DQb
VSS
L
DQb
NC
NC
M
VDDQ
DQb
VSS
N
DQb
NC
VSS
P
NC
DQPb
VSS
R
NC
A
MODE
T
A
A
A
U
VDDQ
TMS
TDI
4M x 18 (TOP VIEW)
4
A
ADV
VDD
NC
CE
OE
A
WE
VDD
CLK
NC
CKE
A1*
A0*
VDD
A
TCK
5
A
A
A
VSS
VSS
VSS
NC
VSS
NC
VSS
BWa
VSS
VSS
VSS
NC
A
TDO
6
A
CE2
A
DQPa
NC
DQa
NC
DQa
VDD
NC
DQa
NC
DQa
NC
A
A
NC
7
VDDQ
NC
NC
NC
DQa
VDDQ
DQa
NC
VDDQ
DQa
NC
VDDQ
NC
DQa
NC
ZZ
VDDQ
Note: A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
Pin Name
A
Synchronous Address Inputs
A0, A1
Synchronous Burst Address Inputs
ADV
Synchronous Burst Address Advance/
Load
WE
Synchronous Read/Write Control Input
CLK
Synchronous Clock
CKE
Synchronous Clock Enable
CE
Synchronous Chip Select
CE2
Synchronous Chip Select
CE2
Synchronous Chip Select
BWa-BWb
Synchronous Byte Write Inputs
OE Asynchronous Output Enable
ZZ
Asynchronous Power Sleep
Mode
MODE Burst Sequence Selection
TCK, TDO JTAG Pins
TMS, TDI
Vdd Power Supply
Vss Ground
NC
DQa-DQb
No Connect
Synchronous Data Inputs/Outputs
DQPa-DQPb Synchronous Parity Data
Inputs/Outputs
Vddq
I/O Power Supply
Integrated Silicon Solution, Inc. — www.issi.com
7
Rev. A
8/4/2014