IS61LV2568L_08 Datasheet, PDF (9/14 Pages) Integrated Silicon Solution, Inc – 256K x 8 HIGH-SPEED CMOS STATIC RAM

IS61LV2568L
AC WAVEFORMS
WRITE CYCLE NO. 1^(1,2) (CE Controlled, OE = HIGH or LOW)
t WC
ADDRESS
CE
WE
DOUT
DIN
t SA
VALID ADDRESS
t SCE
t HA
DATA UNDEFINED
t AW
t PWE1
t PWE2
t HZWE
HIGH-Z
t LZWE
t SD
t HD
DATAIN VALID
CE_WR1.eps
Note:
1. The internal Write time is defined by the overlap of CE = LOW and WE = LOW. All signals must be in valid states to initiate a
Write, but any can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or
falling edge of the signal that terminates the Write.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
9
Rev. D
04/28/08