IS61LV2568L_08 Datasheet, PDF (10/14 Pages) Integrated Silicon Solution, Inc – 256K x 8 HIGH-SPEED CMOS STATIC RAM

IS61LV2568L
AC WAVEFORMS
WRITE CYCLE NO. 2⁽¹⁾ (WE Controlled, OE = HIGH during Write Cycle)
ADDRESS
OE
t WC
VALID ADDRESS
t HA
CE LOW
WE
DOUT
t SA
DATA UNDEFINED
t AW
t PWE1
t HZWE
HIGH-Z
t LZWE
DIN
t SD
t HD
DATAIN VALID
CE_WR2.eps
Note:
1. The internal Write time is defined by the overlap of CE = LOW and WE = LOW. All signals must be in valid states to initiate a Write, but any
can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that
terminates the Write.
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
ADDRESS
OE ^LOW
t WC
VALID ADDRESS
t HA
CE _LOW
WE
DOUT
t SA
DATA UNDEFINED
DIN
t AW
t PWE2
t HZWE
HIGH-Z
t LZWE
t SD
t HD
DATAIN VALID
CE_WR3.eps
Note:
1. The internal Write time is defined by the overlap of CE = LOW and WE = LOW. All signals must be in valid states to initiate a Write, but any
can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that
terminates the Write.
10
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. D
04/28/08