IS61VPS25672A Datasheet, PDF (8/35 Pages) Integrated Silicon Solution, Inc – 256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

IS61VPS25672A, IS61LPS25672A
IS61VPS51236A, IS61LPS51236A,IS61VPS102418A,IS61LPS102418A
165 PBGA PACKAGE PIN CONFIGURATION
1M X 18 (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
A
NC
A
CE
BWb
NC
CE2
BWE ADSC ADV
A
A
B
NC
A
CE2
NC
BWa
CLK
GW
OE
ADSP A
NC
C
NC
NC
VDDQ
Vss
Vss
Vss
Vss
Vss
VDDQ
NC
DQPa
D
NC
DQb
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
NC
DQa
E
NC
DQb
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
NC
DQa
F
NC
DQb
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
NC
DQa
G
NC
DQb
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
NC
DQa
H
NC
Vss
NC
VDD
Vss
Vss
Vss
VDD
NC
NC
ZZ
J
DQb
NC
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQa
NC
K
DQb
NC
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQa
NC
L
DQb
NC
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQa
NC
M
DQb
NC
VDDQ
VDD
Vss
Vss
Vss
VDD
VDDQ
DQa
NC
N
DQPb NC
VDDQ
Vss
NC
A
Vss
Vss
VDDQ
NC
NC
P
NC
NC
A
A
TDI
A1*
TDO A
A
A
A
R
MODE NC
A
A
TMS A0*
TCK A
A
A
A
Note: * A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
ADSP
ADSC
GW
CLK
CE, CE2, CE2
BWx (x=a,b)
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address
Advance
Address Status Processor
Address Status Controller
Global Write Enable
Synchronous Clock
Synchronous Chip Select
Synchronous Byte Write
Controls
Symbol
BWE
OE
ZZ
MODE
TCK, TDO
TMS, TDI
NC
DQx
DQPx
VDD
VDDQ
Vss
Pin Name
Byte Write Enable
Output Enable
Power Sleep Mode
Burst Sequence Selection
JTAG Pins
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
3.3V/2.5V Power Supply
Isolated Output Power Supply
3.3V/2.5V
Ground
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. N
02/12/2010