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IS61VPS25672A Datasheet, PDF (25/35 Pages) Integrated Silicon Solution, Inc – 256K x 72, 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM | |||
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IS61VPS25672A, IS61LPS25672A
IS61VPS51236A, IS61LPS51236A,IS61VPS102418A,IS61LPS102418A
TAP Electrical Characteristics Over the Operating Range(1,2)
Symbol
Parameter
Test Conditions
VOH1
Output HIGH Voltage
IOH = â2.0 mA
VOH2
Output HIGH Voltage
IOH = â100 µA
VOL1
Output LOW Voltage
IOL = 2.0 mA
VOL2
Output LOW Voltage
IOL = 100 µA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IX
Input Leakage Current
VSS ⤠V I ⤠VDDQ
Notes:
1. All Voltage referenced to Ground.
2. Overshoot: VIH (AC) ⤠VDD +1.5V for t ⤠tTCYC/2,
Undershoot: VIL (AC) ⤠0.5V for t ⤠tTCYC/2,
Power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms.
Min.
1.7
2.1
â
â
1.7
â0.3
â10
Max.
â
â
0.7
0.2
VDD +0.3
0.7
10
Units
V
V
V
V
V
V
µA
TAP AC ELECTRICAL CHARACTERISTICS(1,2) (OVER OPERATING RANGE)
Symbol Parameter
Min.
Max.
Unit
tTCYC
TCK Clock cycle time
100
â
ns
fTF
TCK Clock frequency
â
10
MHz
tTH
TCK Clock HIGH
40
â
ns
tTL
TCK Clock LOW
40
â
ns
tTMSS TMS setup to TCK Clock Rise
10
â
ns
tTDIS
TDI setup to TCK Clock Rise
10
â
ns
tCS
Capture setup to TCK Rise
10
â
ns
tTMSH TMSholdafterTCKClockRise
10
â
ns
tTDIH
TDI Hold after Clock Rise
10
â
ns
tCH
Capture hold after Clock Rise
10
â
ns
tTDOV
TCK LOW to TDO valid
â
20
ns
tTDOX TCK LOW to TDO invalid
0
â
ns
Notes:
1. Both tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
2. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
Integrated Silicon Solution, Inc. â 1-800-379-4774
25
Rev. N
02/12/2010
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