IS61NLP25672 Datasheet, PDF (8/35 Pages) Integrated Silicon Solution, Inc – 256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE (NO WAIT) STATE BUS SRAM

IS61NLP25672/IS61NVP25672
IS61NLP51236/IS61NVP51236
IS61NLP102418/IS61NVP102418
STATE DIAGRAM
READ
BEGIN
READ
DS
READ
READ
WRITE
DS
WRITE
BEGIN
WRITE
ISSI ^®
WRITE
READ _BURST
BURST
BURST
READ
DESELECT
BURST WRITE
DS
BURST
DS
WRITE
DS
READ
BURST
WRITE
BURST
SYNCHRONOUS TRUTH TABLE⁽¹⁾
Operation
Address
Used
CE CE2 CE2 ADV WE BWx OE CKE CLK
Not Selected
N/A
H
X
X
L
X
X
X
L
↑
Not Selected
N/A
X
L
X
L
X
X
X
L
↑
Not Selected
N/A
X
X
H
L
X
X
X
L
↑
Not Selected Continue
N/A
X
X
X
H
X
X
X
L
↑
Begin Burst Read
External Address L
H
L
L
H
X
L
L
↑
Continue Burst Read
Next Address
X
X
X
H
X
X
L
L
↑
NOP/Dummy Read
External Address L
H
L
L
H
X
H
L
↑
Dummy Read
Next Address
X
X
X
H
X
X
H
L
↑
Begin Burst Write
External Address L
H
L
L
L
L
X
L
↑
Continue Burst Write
Next Address
X
X
X
H
X
L
X
L
↑
NOP/Write Abort
N/A
L
H
L
L
L
H
X
L
↑
Write Abort
Next Address
X
X
X
H
X
H
X
L
↑
Ignore Clock
Current Address X
X
X
X
X
X
X
H
↑
Notes:
1. "X" means don't care.
2. The rising edge of clock is symbolized by ↑
3. A continue deselect cycle can only be entered if a deselect cycle is executed first.
4. WE = L means Write operation in Write Truth Table.
WE = H means Read operation in Write Truth Table.
5. Operation finally depends on status of asynchronous pins (ZZ and OE).
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. G
07/10/06