IS61NLF102436A Datasheet, PDF (8/23 Pages) Integrated Silicon Solution, Inc – STATE BUS SRAM

IS61NLF102436A/IS61NVF102436A
IS61NLF204818A/IS61NVF204818A 
ASYNCHRONOUS TRUTH TABLE⁽¹⁾
Operation
ZZ
OE
I/O STATUS
Sleep Mode
H
X
High-Z
Read
L
L
L
H
DQ
High-Z
Write
L
X
Din, High-Z
Deselected
L
X
High-Z
Notes:
1. X means "Don't Care".
2. For write cycles following read cycles, the output buffers must be disabled with OE, otherwise data
bus contention will occur.
3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time.
4. Deselected means power Sleep Mode where stand-by current depends on cycle time.
WRITE TRUTH TABLE (x18)
Operation
WE
BWa
BWb
READ
H
X
X
WRITE BYTE a
L
L
H
WRITE BYTE b
L
H
L
WRITE ALL BYTEs
L
L
L
WRITE ABORT/NOP
L
H
H
Notes:
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
WRITE TRUTH TABLE (x36)
Operation
WE
BWa BWb BWc BWd
READ
H
X
X
X
X
WRITE BYTE a
L
L
H
H
H
WRITE BYTE b
L
H
L
H
H
WRITE BYTE c
L
H
H
L
H
WRITE BYTE d
L
H
H
H
L
WRITE ALL BYTEs
L
L
L
L
L
WRITE ABORT/NOP
L
H
H
H
H
Notes:
1. X means "Don't Care".
2. All inputs in this table must beet setup and hold time around the rising edge of CLK.
INTERLEAVED BURST ADDRESS TABLE (MODE = Vdd or NC)
External Address
A1  A0
00
01
10
11
1st Burst Address
A1  A0
01
00
11
10
2nd Burst Address
A1  A0
10
11
00
01
3rd Burst Address
A1  A0
11
10
01
00
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev.  B
06/09/08