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IS61NLF102436A Datasheet, PDF (5/23 Pages) Integrated Silicon Solution, Inc – STATE BUS SRAM
IS61NLF102436A/IS61NVF102436A
IS61NLF204818A/IS61NVF204818A 
165-PIN PBGA PACKAGE CONFIGURATION 2M x 18 (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
A NC
A
CE BWb
NC CE2 CKE ADV
A
A
A
B NC
A
CE2 NC
BWa CLK
WE
OE
A
A
NC
C NC
NC VDDQ Vss
Vss Vss
Vss
Vss VDDQ NC DQPa
D NC DQb VDDQ VDD
Vss Vss
Vss
VDD
VDDQ
NC
DQa
E NC DQb VDDQ VDD
Vss Vss
Vss
VDD VDDQ
NC
DQa
F
NC
DQb VDDQ VDD
Vss Vss
Vss
VDD
VDDQ
NC
DQa
G
NC
DQb
VDDQ VDD
H NC VDD
NC VDD
Vss
Vss
Vss
VDD
VDDQ
NC
DQa
Vss
Vss
Vss
VDD
NC
NC
ZZ
J DQb
NC
VDDQ VDD
Vss
Vss
Vss
VDD
VDDQ
DQa
NC
K DQb NC VDDQ VDD
Vss
Vss
Vss
VDD
VDDQ
DQa
NC
L DQb NC VDDQ VDD
M DQb NC VDDQ VDD
Vss Vss
Vss Vss
Vss
VDD
VDDQ
DQa NC
Vss
VDD VDDQ
DQa
NC
N DQPb NC VDDQ Vss
NC
NC
NC
Vss VDDQ
NC
NC
P NC NC
A
A
TDI
A1* TDO
A
A
A
NC
R MODE A
A
A
TMS
A0*
TCK
A
A
A
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
Pin Name
A
Address Inputs
A0, A1
Synchronous Burst Address Inputs
ADV
Synchronous Burst Address Advance/
Load
WE
Synchronous Read/Write Control
Input
CLK
Synchronous Clock
CKE
Clock Enable
CE
Synchronous Chip Select
CE2
Synchronous Chip Select
CE2
Synchronous Chip Select
BWx (x=a,b) Synchronous Byte Write Inputs
OE
Output Enable
ZZ
Power Sleep Mode
MODE
TCK, TDI
TDO, TMS
VDD
NC
DQx
DQPx
VDDQ
Vss
Burst Sequence Selection
JTAG Pins
3.3V/2.5V Power Supply
No Connect
Data Inputs/Outputs
Parity Data I/O
Isolated output Power Supply
3.3V/2.5V
Ground
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
5
Rev.  B
06/09/08