IS61LV256AL Datasheet, PDF (8/13 Pages) Integrated Silicon Solution, Inc – 32K x 8 LOW VOLTAGE CMOS STATIC RAM

IS61LV256AL
WRITE CYCLE NO. 2 (WE Controlled, OE is HIGH During Write Cycle) ^(1,2)
ADDRESS
OE
t WC
VALID ADDRESS
t HA
ISSI ^®
CE ^LOW
WE
DOUT
t SA
DATA UNDEFINED
t AW
t PWE1
t HZWE
DIN
HIGH-Z
t LZWE
t SD
t HD
DATAIN VALID
WRITE CYCLE NO. 3 (WE Controlled, OE is LOW During Write Cycle) ⁽¹⁾
t WC
ADDRESS
VALID ADDRESS
t HA
OE ^LOW
CE_WR2.eps
CE _LOW
WE
DOUT
t SA
DATA UNDEFINED
t AW
t PWE2
t HZWE
HIGH-Z
t LZWE
t SD
t HD
DIN
DATAIN VALID
CE_WR3.eps
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE > VIH.
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/17/06