IS61LV12824 Datasheet, PDF (8/13 Pages) Integrated Silicon Solution, Inc – 128K x 24 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY

IS61LV12824
ISSI ^®
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,3) (Over Operating Range)
Symbol Parameter
-8
-10
Min. Max.
Min. Max.
Unit
tWC
Write Cycle Time
8—
10 —
ns
tSCE
CE1, CE2 to Write End
7—
8
—
ns
tSCE2
CE2 to Write End
7—
8
—
tAW
Address Setup Time
to Write End
7—
8
—
ns
tHA
Address Hold from Write End
0—
0
—
ns
tSA
Address Setup Time
0—
0
—
ns
tPWE1
WE Pulse Width (OE = HIGH)
6—
8
—
ns
tPWE2
WE Pulse Width (OE = LOW)
6—
9
—
ns
tSD
Data Setup to Write End
4.5 —
5
—
ns
tHD
Data Hold from Write End
0—
0
—
ns
tHZWE⁽²⁾
WE LOW to High-Z Output
— 3.5
— 3.5
ns
tLZWE⁽²⁾
WE HIGH to Low-Z Output
3—
3
—
ns
Notes:
1. Test conditions assume signal transition times of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE1, CE2 LOW, CE2 HIGH and WE LOW. All signals must be in valid
states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are
referenced to the rising or falling edge of the signal that terminates the write.
8
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
06/22/05