IS61LV12824 Datasheet, PDF (10/13 Pages) Integrated Silicon Solution, Inc – 128K x 24 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY

IS61LV12824
ISSI ^®
WRITE CYCLE NO. 3⁽¹⁾ (WE Controlled: OE I S LOW DURING WRITE CYLE)
t WC
ADDRESS
VALID ADDRESS
t HA
OE ^LOW
CE1 _LOW
HIGH
CE2
WE
DOUT
t SA
DATA UNDEFINED
t AW
t PWE2
t HZWE
HIGH-Z
t LZWE
t SD
t HD
DIN
DATAIN VALID
CE2_WR3.eps
Note:
1. The internal Write time is defined by the overlap of CE1 and CE2 = LOW, CE2 = HIGH and WE = LOW. All signals must be
in valid states to initiate a Write, but any can be deasserted to terminate the Write. The Data Input Setup and Hold timing is
referenced to the rising or falling edge of the signal that terminates the Write.
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
06/22/05