IS61LV12824 Datasheet, PDF (7/13 Pages) Integrated Silicon Solution, Inc – 128K x 24 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY

IS61LV12824
ISSI ^®
AC WAVEFORMS
READ CYCLE NO. 1^(1,2) (Address Controlled) (CE1 = CE2 = OE = VIL; CE2 = VIH)
t RC
ADDRESS
DOUT
t AA
t OHA
PREVIOUS DATA VALID
t OHA
DATA VALID
READ CYCLE NO. 2^(1,3)
ADDRESS
OE
CS1
t RC
t AA
t DOE
t LZOE
t OHA
t HZOE
1
2
3
READ1.eps
4
5
6
7
CS2
DOUT
t LZCS1
t LZCS2
HIGH-Z
t ACS1
t ACS2
DATA VALID
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE1, CE2 = VIL. CE2 = VIH.
3. Address is valid prior to or coincident with CE1, CE2 LOW and CE2 HIGH transition.
8
t HZCS1
t HZCS2
9
CS2_RD2.eps
10
11
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
7
Rev. D
06/22/05