IS61LV10248 Datasheet, PDF (8/16 Pages) Integrated Silicon Solution, Inc – 1M x 8 HIGH-SPEED CMOS STATIC RAM

IS61LV10248
ISSI ^®
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,3) (Over Operating Range)
Symbol
tWC
tSCE
tAW
tHA
tSA
tPWE1
tPWE2
tSD
tHD
tHZWE⁽²⁾
tLZWE⁽²⁾
Parameter
Write Cycle Time
CE to Write End
Address Setup Time
to Write End
Address Hold from Write End
Address Setup Time
WE Pulse Width
WE Pulse Width (OE = LOW)
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
-8
-10
Min. Max.
Min. Max.
Unit
8
—
10 —
ns
6.5 —
8
—
ns
6.5 —
8
—
ns
0
—
0
—
ns
0
—
0
—
ns
6.5 —
8
—
ns
8
—
10 —
ns
5
—
6
—
ns
0
—
0
—
ns
— 3.5
—
5
ns
2
—
2
—
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0V to 3.0V
and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the write.
8
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. C
04/13/06