IS62LV256AL Datasheet, PDF (7/14 Pages) Integrated Silicon Solution, Inc – 32K x 8 LOW VOLTAGE CMOS STATIC RAM

IS65LV256AL
IS62LV256AL
ISSI ^®
WRITE CYCLE SWITCHING CHARACTERISTICS^(1,3) (Over Operating Range)
Symbol
tWC
tSCE
tAW
tHA
tSA
tPWE⁽⁴⁾
tSD
tHD
tHZWE⁽²⁾
tLZWE⁽²⁾
Parameter
Write Cycle Time
CE to Write End
Address Setup Time to Write End
Address Hold from Write End
Address Setup Time
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE LOW to High-Z Output
WE HIGH to Low-Z Output
-20 ns
Min. Max.
20
—
15
—
14
—
0
—
0
—
14
—
13
—
0
—
—
8
0
—
-45 ns
Min. Max.
45
—
35
—
25
—
0
—
0
—
25
—
20
—
0
—
— 20
0
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
4. Tested with OE HIGH.
AC WAVEFORMS
WRITE CYCLE NO. 1 (WE Controlled)^(1,2)
ADDRESS
CE
WE
DOUT
DIN
tWC
tSCE
tHA
tAW
tPWE
tSA
tHZWE
DATA UNDEFINED
HIGH-Z
tLZWE
tSD
tHD
DATA-IN VALID
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
7
Rev. A
03/17/06