IS62C1024AL Datasheet, PDF (7/11 Pages) Integrated Silicon Solution, Inc – 128K x 8 LOW POWER CMOS STATIC RAM

IS62C1024AL
IS65C1024AL
AC WAVEFORMS
WRITE CYCLE NO. 1 (WE Controlled)^(1,2)
ADDRESS
CE1
CE2
WE
DOUT
DIN
tWC
tSCE1
tHA
tSCE2
tAW
tPWE⁽⁴⁾
tSA
tHZWE
DATA UNDEFINED
HIGH-Z
tLZWE
tSD
tHD
DATA-IN VALID
ISSI ^®
WRITE CYCLE NO. 2 (CE1, CE2 Controlled)^(1,2)
ADDRESS
CE1
CE2
WE
DOUT
DIN
tSA
tWC
tSCE1
tHA
tSCE2
tAW
tPWE⁽⁴⁾
tHZWE
DATA UNDEFINED
HIGH-Z
tLZWE
tSD
tHD
DATA-IN VALID
Notes:
1. The internal write time is defined by the overlap of CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE = VIH.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
7
Rev. C
01/24/05