IS80LV52 Datasheet, PDF (38/48 Pages) Integrated Silicon Solution, Inc – CMOS SINGLE CHIP LOW VOLTAGE 8-BIT MICROCONTROLLER

IS80LV52
IS80LV32
ROM Verification
The address of the program memory location to be read
is applied to Port 1 and pins P2.4-P2.0. The other pins
should be held at the “Verify” level are indicated in Figure
26. The contents of the addressed locations exits on Port
0. External pullups are required on Port 0 for this operation.
Figure 26 shows the setup to verify the program memory.
ISSI ^®
A7-A0
P1
A12-A8
1
1
1
0
0
0
P2.4-P2.0
RST
EA
ALE
PSEN
P2.7
P2.6
XTAL1
4-6 MHz
XTAL2
GND
+ 5V
Vcc
10K x 8
P0
PGM
DATA
Figure 27. ROM Verification
38
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION MC019-0A
10/01/98