IS80LV52 Datasheet, PDF (23/48 Pages) Integrated Silicon Solution, Inc – CMOS SINGLE CHIP LOW VOLTAGE 8-BIT MICROCONTROLLER

IS80LV52
IS80LV32
ISSI ^®
More About Mode 0
Serial data enters and exits through RXD. TXD outputs
the shift clock. Eight data bits are transmitted/received,
with the LSB first. The baud rate is fixed at 1/12 the
oscillator frequency.
Figure 15 shows a simplified functional diagram of the
serial port in Mode 0 and associated timing.
Transmission is initiated by any instruction that uses
SBUF as a destination register. The "write to SBUF"
signal at S6P2 also loads a 1 into the ninth position of the
transmit shift register and tells the TX Control block to
begin a transmission. The internal timing is such that one
full machine cycle will elapse between "write to SBUF"
and activation of SEND.
SEND transfer the output of the shift register to the
alternate output function line of P3.0, and also transfers
SHIFT CLOCK to the alternate output function line of
P3.1. SHIFT CLOCK is low during S3, S4, and S5 of every
machine cycle, and high during S6, S1, and S2. At S6P2
of every machine cycle in which SEND is active, the
contents of the transmit shift register are shifted one
position to the right.
As data bits shift out to the right, 0s come in from the left.
When the MSB of the data byte is at the output position of
the shift register, the 1 that was initially loaded into the
ninth position is just to the left of the MSB, and all positions
to the left of that contain 0s. This condition flags the TX
Control block to do one last shift, then deactivate SEND
and set TI. Both of these actions occur at S1P1 of the tenth
machine cycle after "write to SBUF."
Reception is initiated by the condition REN = 1 and
RI = 0. At S6P2 of the next machine cycle, the RX Control
unit writes the bits 11111110 to the receive shift register
and activates RECEIVE in the next clock phase.
RECEIVE enables SHIFT CLOCK to the alternate output
function line of P3.1. SHIFT CLOCK makes transitions at
S3P1 and S6P1 of every machine cycle. At S6P2 of every
machine cycle in which RECEIVE is active, the contents
of the receive shift register are shifted on position to the
left. The value that comes in from the right is the value that
was sampled at the P3.0 pin at S5P2 of the same machine
cycle.
As data bits come in from the right, 1s shift out to the left.
When the 0 that was initially loaded into the right-most
position arrives at the left-most position in the shift register,
it flags the RX Control block to do one last shift and load
SBUF. At S1P1 of the 10th machine cycle after the write
to SCON that cleared RI, RECEIVE is cleared and RI is
set.
More About Mode 1
Ten bits are transmitted (through TXD), or received
(through RXD): a start bit (0), eight data bits (LSB first),
and a stop bit (1). On receive, the stop bit goes into RB8
in SCON. In the IS80LV52/32 the baud rate is determined
either by the Timer 1 overflow rate, the Timer 2 overflow
rate, or both. In this case, one Timer is for transmit, and the
other is for receive.
Figure 16 shows a simplified functional diagram of the
serial port in Mode 1 and associated timings for transmit
and receive.
Transmission is initiated by any instruction that uses
SBUF as a destination register.
The "write to =SBUF" signal also loads a 1 into the ninth
bit position of the transmit shift register and flags the TX
control unit that a transmission is requested. Transmission
actually commences at S1P1 of the machine cycle following
the next rollover in the divide-by-16 counter. Thus, the bit
times are synchronized to the divide-by-16 counter, not to
the "write to SBUF" signal.
The transmission begins when SEND is activated, which
puts the start bit at TXD. One bit time later, DATA is
activated, which enables the output bit of the transmit shift
register to TXD. The first shift pulse occurs one bit time
after that.
As data bits shift out to the right, 0s are clocked in from the
left. When the MSB of the data byte is at the output
position of the shift register, the 1 that was initially loaded
into the ninth position is just to the left of the MSB, and all
positions to the left of that contain 0s. This condition flags
the TX Control unit to do one last shift, then deactivate
SEND and set TI. This occurs at the tenth divide-by-16
rollover after "write to SBUF".
Reception is initiated by a 1-to-0 transition detected at
RXD. For this purpose, RXD is sampled at a rate of 16
times the established baud rate. When a transition is
detected, the divide-by-16 counter is immediately reset,
and 1FFH is written into the input shift register. Resetting
the divide-by-16 counter aligns its rollovers with the
boundaries of the incoming bit times.
The 16 states of the counter divide each bit time into 16th.
At the seventh, eighth, and ninth counter states of each bit
time, the bit detector samples the value of RXD. The value
accepted is the value that was seen in at least two of the
three samples. This is done to reject noise. In order to
reject false bits, if the value accepted during the first bit
time is not 0, the receive circuits are reset and the unit
continues looking for another 1-to-0 transition. If the start
bit is valid, it is shifted into the input shift register, and
reception of the rest of the frame proceeds.
Integrated Silicon Solution, Inc. — 1-800-379-4774
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ADVANCE INFORMATION MC019-0A
10/01/98