IS80LV52 Datasheet, PDF (12/48 Pages) Integrated Silicon Solution, Inc – CMOS SINGLE CHIP LOW VOLTAGE 8-BIT MICROCONTROLLER

IS80LV52
IS80LV32
ISSI ^®
IP:
Interrupt Priority Register. Bit Addressable.
7
65
4
3
2
10
— — PT2 PS PT1 PX1 PT0 PX0
Register Description:
— IP.7 Not implemented, reserve for future use⁽³⁾
— IP.6 Not implemented, reserve for future use⁽³⁾
PT2 IP.5 Defines Timer 2 interrupt priority level
PS IP.4 Defines Serial Port interrupt priority level
PT1 IP.3 Defines Timer 1 interrupt priority level
PX1 IP.2 Defines External Interrupt 1 priority level
PT0 IP.1 Defines Timer 0 interrupt priority level
PX0 IP.0 Defines External Interrupt 0 priority level
Notes:
1. In order to assign higher priority to an interrupt the
coresponding bit in the IP register must be set to 1. While an
interrupt service is in progress, it cannot be interrupted by a
lower or same level interrupt.
2. Priority within level is only to resolve simultaneous requests
of the same priority level. From high to low, interrupt sources
are listed below:
IE0
TF0
IE1
TF1
RI or TI
TF2 or EXF2
3. User software should not write 1s to reserved bits. These bits
may be used in future products to invoke new features.
TCON:
Timer/Counter Control Register. Bit Addressable
7
65
4
3
2
10
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Register Description:
TF1 TCON.7 Timer 1 overflow flag. Set by hardware
when the Timer/Counter 1 overflows.
Cleared by hardware as processor
vectors to the interrupt service routine.
TR1 TCON.6 Timer 1 run control bit. Set/Cleared by
software to turn Timer/Counter 1 ON/
OFF.
TF0 TCON.5 Timer 0 overflow flag. Set by hardware
when the Timer/Counter 0 overflows.
Cleared by hardware as processor
vectors to the interrupt service routine.
TR0 TCON.4 Timer 0 run control bit. Set/Cleared by
software to turn Timer/Counter 0 ON/
OFF.
IE1 TCON.3 External Interrupt 1 edge flag. Set by
hardware when the External Interrupt
edge is detected. Cleared by hardware
when interrupt is processed.
IT1 TCON.2 Interrupt 1 type control bit. Set/Cleared
by software specify falling edge/low
level triggered External Interrupt.
IE0 TCON.1 External Interrupt 0 edge flag. Set by
hardware when the External Interrupt
edge is detected. Cleared by hardware
when interrupt is processed.
IT0 TCON.0 Interrupt 0 type control bit. Set/Cleared
by software specify falling edge/low
level triggered External Interrupt.
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
ADVANCE INFORMATION MC019-0A
10/01/98